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| author | quic_hchandel <quic_hchandel@quicinc.com> | 2025-02-24 21:34:29 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-02-24 08:04:29 -0800 |
| commit | 538b898a836ac6efc3b0ec12cf27b511608d2e64 (patch) | |
| tree | 2dab95a68e3a38910d750e98324d37bc295a309c /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | b66ec64b5b634cbf760d69d1629e462268aa1cbd (diff) | |
| download | llvm-538b898a836ac6efc3b0ec12cf27b511608d2e64.zip llvm-538b898a836ac6efc3b0ec12cf27b511608d2e64.tar.gz llvm-538b898a836ac6efc3b0ec12cf27b511608d2e64.tar.bz2 | |
[RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (#124706)
This extension adds eight 48 bit large arithmetic instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 53208b4..8c07d87 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -767,6 +767,8 @@ DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size, for (size_t i = Size; i-- != 0;) { Insn += (static_cast<uint64_t>(Bytes[i]) << 8 * i); } + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcilia, DecoderTableXqcilia48, + "Qualcomm uC Large Immediate Arithmetic 48bit"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcilo, DecoderTableXqcilo48, "Qualcomm uC Large Offset Load Store 48bit"); |