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| author | Brandon Wu <brandon.wu@sifive.com> | 2023-11-03 10:08:26 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-03 10:08:26 +0800 |
| commit | 945d2e6e603dd9cc5d155a3a34b67ecf17b91b68 (patch) | |
| tree | 5e2ce0d4decfb256d4c3aaca6347496f7311523d /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 801a30aa8ff1c2655d49a0fa88ff72f4e7056ab9 (diff) | |
| download | llvm-945d2e6e603dd9cc5d155a3a34b67ecf17b91b68.zip llvm-945d2e6e603dd9cc5d155a3a34b67ecf17b91b68.tar.gz llvm-945d2e6e603dd9cc5d155a3a34b67ecf17b91b68.tar.bz2 | |
[RISCV] Support Xsfvfwmaccqqq extensions (#68296)
Bfloat16 Matrix Multiply Accumulate Instruction
https://sifive.cdn.prismic.io/sifive/c391d53e-ffcf-4091-82f6-c37bf3e883ed_xsfvfwmaccqqq-spec.pdf
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 9bd7cac..fd9e278 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -550,6 +550,9 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, TRY_TO_DECODE_FEATURE( RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32, "SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table"); + TRY_TO_DECODE_FEATURE( + RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32, + "SiFive Matrix Multiplication Instruction opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32, "Sifive CIE custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip, |