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| author | LiaoChunyu <chunyu@iscas.ac.cn> | 2023-11-16 09:34:38 +0800 |
|---|---|---|
| committer | LiaoChunyu <chunyu@iscas.ac.cn> | 2023-11-16 09:46:11 +0800 |
| commit | 71a7108ee91a522251ff37638e26158570c1e2a5 (patch) | |
| tree | bd98411d09d17f4ca89143ae47634f644d7b402f /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 10cc3a8556a8ff9557890c96de162cb2c09669e2 (diff) | |
| download | llvm-71a7108ee91a522251ff37638e26158570c1e2a5.zip llvm-71a7108ee91a522251ff37638e26158570c1e2a5.tar.gz llvm-71a7108ee91a522251ff37638e26158570c1e2a5.tar.bz2 | |
[RISCV][MC] MC layer support for xcvmem and xcvelw extensions
This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Several other extensions have been merged.
Spec:
https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst
Contributors: @CharKeaney, @jeremybennett, @lewis-revill, Nandni Jamnadas, @PaoloS, @simoncook, @xmj, @realqhc, @melonedo, @adeelahmad81299
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D158824
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index f3a4945..53e2b6b 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -353,6 +353,9 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder); +static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address, + const MCDisassembler *Decoder); + static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder); @@ -450,6 +453,15 @@ static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm, return MCDisassembler::Success; } +static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address, + const MCDisassembler *Decoder) { + uint32_t Rs1 = fieldFromInstruction(Insn, 0, 5); + uint32_t Rs2 = fieldFromInstruction(Insn, 5, 5); + DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder); + DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder); + return MCDisassembler::Success; +} + // spimm is based on rlist now. static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) { @@ -561,8 +573,12 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip, DecoderTableXCVbitmanip32, "CORE-V Bit Manipulation custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32, + "CORE-V Event load custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32, "CORE-V MAC custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32, + "CORE-V MEM custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32, "CORE-V ALU custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32, |