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Fix: Vector CSRs exist without any vector extension since a484f6e
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https://github.com/riscv-software-src/riscv-isa-sim/commit/66c4853bdc5b22bf4c4b364218c713e3f1e487f3
The require_vector_vs, i.e., sstatus_csr_t::enabled(SSTATUS_VS), was
expected to provide has_any_vector() check [1]. Unfortunately, a
previous commit [2] made the sstatus_csr_t::enabled(SSTATUS_VS) true
without any vector extension.
The previous commit [2] was for P-extension, which has been removed from
Spike [3].
This commit reverts the commit [2] and corrects require_vector_vs [1].
[1] https://github.com/riscv-software-src/riscv-isa-sim/pull/1701/commits/a484f6efc5f50836bb8d846180dfbb9786d09ae2
[2] https://github.com/riscv-software-src/riscv-isa-sim/commit/66c4853bdc5b22bf4c4b364218c713e3f1e487f3
[3] https://github.com/riscv-software-src/riscv-isa-sim/pull/1660
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The senvcfg.SSE will read (only) as zero when menvcfg.SSE is 0
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Fix zkr
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Fix ePMP checking on hlvx instructions
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The hlvx instruction must grant PMP permissions of both execution and
reading. Thus, with ePMP (mseccfg.MML==1), the hlvx instructions are
only permitted with pmpcfg.RWXL=0111 from M-mode.
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excp: support hardware_error_exception delegation
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ssqosid: modify permission check condition for srmcfg
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enable M -> S and HS -> VU/VS delegation
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The srmcfg csr number is 0x181 which is a S-mode csr
The patche uses independant permission check to make the csr available
even there is no S-mode
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The debug spec 1.0.0-rc3 deprecates the dcsr.halt and lets the bit
become dcsr.nmip.
This commit separates the halt variable from the dcsr.nmip and
designates it as an internal variable for halt_on_reset (-H).
Additionally, this commit removes the notifying comment about the
deprecated dcsr.halt in the main loop.
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Rename DCSR_STOPCYCLE to DCSR_STOPCOUNT
Rename DCSR_HALT to DCSR_NMIP
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isa_parser should already require any Zvef or Zved extensions
imply F/D
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Accidentally removed in c9468f6e02.
See #1660.
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Smstateen: Ignore writes to read-only hstateen*[n] bits when mstateen*[n]=0
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The specification states that writes to read-only bits in a RW CSR are
ignored. The hstateen*[n] bits are read-only when mstateen*[n]=0. This
PR proposes ignoring writes to read-only hstateen*[n] bits when
mstateen*[n]=0 instead of writing the bits to 0.
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1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name.
2. Add new software exception with tval 3 for shadow stack.
3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d.
4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding.
5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page.
6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag.
7. Check special pte(xwr=010) of SS page.
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The henvcfg fields, i.e., PBMTE, STCE, and ADUE, are read-only 0 when
the corresponding bits in menvcfg are 0. Besides the reading behavior,
the spec also specified the writing behavior, i.e., ignoring writes.
This commit ignores writes to the henvcfg fields when read-only 0.
Reference: https://github.com/riscv/riscv-isa-manual/issues/1312
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Zicfilp being enabled
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Teach Sstc to respect xenvcfg.STCE
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interrupts or CSR hgeip bits
The H extension defines that bits VSEIP, VSTIP, and VSSIP of hvip are
writable. (The other bits of hvip are read-only 0.) Only hip.VSSIP
(mip.VSSIP) is an alias of hvip.VSSIP. The hip.VSEIP is the logical-OR
of hvip.VSEIP, selected bit of hgeip by hstatus.VGEIN, and
platform-specific external interrupt signals to VS-level, e.g., from
AIA. The hip.VSTIP is the logical-OR of hvip.VSTIP and platform-specific
timer interrupt signals to VS-level, e.g., from Sstc. Thus, the read
values of hvip.VSEIP and hvip.VSTIP differ from the ones of hip.VSEIP
and hip.VSTIP (mip.VSEIP and mip.VSTIP). In other words, the hvip isn't
an alias (proxy) of mip.
The current aliasing (proxy) implementation does not provide the desired
behavior for hvip.VSEIP and hvip.VSTIP. An ISA-level behavior difference
is that any platform-specific external and timer interrupt signals
directed to VS-level should not be observable through the hvip. For
instance, the hvip should not observe the virtual timer interrupt signal
from the vstimecmp CSR (Sstc extension), which isn't true in the current
implementation. Additionally, the hvip should not observe the virtual
external interrupt signal from the IMSIC device (AIA extension).
Another ISA-level behavior difference is that the hgeip and
hstatus.VGEIN also should not affect hvip.VSEIP, which isn't true in the
current implementation.
This commit fixes the issue by giving the hvip a specialized class,
hvip_csr_t. The hvip_csr_t aliases the hvip.VSSIP to the mip.VSSIP but
decouples the hvip.VSEIP and hvip.VSTIP from mip.VSEIP and mip.VSTIP.
Additionally, the commit updates the read value of mip to be the
logical-OR of hvip.VSEIP, hvip.VSTIP, and other sources.
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When menvcfg.STCE=0, mip.STIP reverts to its defined behavior as if
unsupporting Sstc extension. When henvcfg.STCE=0, mip.VSTIP reverts
to its defined behavior as if unsupporting Sstc extension. [https://github.com/riscv/riscv-time-compare/issues/5]
The previous Sstc implementation does not respect the xenvcfg.STCE.
In other words, the Sstc may assert mip.STIP (mip.VSTIP) when
menvcfg.STCE=0 (henvcfg.STCE=0), which is a misbehaving.
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Signed-off-by: Ved Shanbhogue <91900059+ved-rivos@users.noreply.github.com>
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modes
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HS-mode
The spec requires menvcfg.STCE=1 on accessing stimecmp or vstimecmp in a
mode other than M-mode. The previous implementation does not check the
permission on accessing vstimecmp in HS-mode. This commit fixes the
issue by moveing the permission check from virtualized_stimecmp_csr_t to
stimecmp_csr_t, which implements the vstimecmp.
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