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| author | Andrew Waterman <andrew@sifive.com> | 2024-07-17 14:59:28 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-07-17 14:59:28 -0700 |
| commit | c0281a17d6473137c243ebd093711adb95024e68 (patch) | |
| tree | d208bcb28806ebb296b43cd7a33bb50254ffbc85 /riscv/csrs.cc | |
| parent | fd141e9a43b752076822f417758c9ae524fa856e (diff) | |
| parent | 08463028d68fe75d1bc59c9f20b9c86f8bd9f460 (diff) | |
| download | riscv-isa-sim-c0281a17d6473137c243ebd093711adb95024e68.zip riscv-isa-sim-c0281a17d6473137c243ebd093711adb95024e68.tar.gz riscv-isa-sim-c0281a17d6473137c243ebd093711adb95024e68.tar.bz2 | |
Merge pull request #1735 from chihminchao/deleg-hw-excp
excp: support hardware_error_exception delegation
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 7fdab94..2bb255d 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -930,6 +930,7 @@ bool medeleg_csr_t::unlogged_write(const reg_t val) noexcept { | (1 << CAUSE_STORE_PAGE_FAULT) | (proc->extension_enabled('H') ? hypervisor_exceptions : 0) | (1 << CAUSE_SOFTWARE_CHECK_FAULT) + | (1 << CAUSE_HARDWARE_ERROR_FAULT) ; return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask)); } |