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| author | Andrew Waterman <andrew@sifive.com> | 2024-02-07 17:57:30 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-02-07 17:57:30 -0800 |
| commit | 3a53c80ade3336b1d46c9db3a6c6be8311c32cc5 (patch) | |
| tree | 0e2df873849ae3b0418987a2abb791eb00f60a5c /riscv/csrs.cc | |
| parent | d4726e1cf542471298f261f792eeb9a5c67e5f49 (diff) | |
| parent | 928743b105becf2bedf704b97d220825690c0c52 (diff) | |
| download | riscv-isa-sim-3a53c80ade3336b1d46c9db3a6c6be8311c32cc5.zip riscv-isa-sim-3a53c80ade3336b1d46c9db3a6c6be8311c32cc5.tar.gz riscv-isa-sim-3a53c80ade3336b1d46c9db3a6c6be8311c32cc5.tar.bz2 | |
Merge pull request #1591 from YenHaoChen/pr-sstc-stce
Teach Sstc to respect xenvcfg.STCE
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 74f07c9..0e8bf6d 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1079,7 +1079,8 @@ void time_counter_csr_t::sync(const reg_t val) noexcept { if (proc->extension_enabled(EXT_SSTC)) { const reg_t mip_val = (shadow_val >= state->stimecmp->read() ? MIP_STIP : 0) | (shadow_val + state->htimedelta->read() >= state->vstimecmp->read() ? MIP_VSTIP : 0); - state->mip->backdoor_write_with_mask(MIP_STIP | MIP_VSTIP, mip_val); + const reg_t mask = ((state->menvcfg->read() & MENVCFG_STCE) ? MIP_STIP : 0) | ((state->henvcfg->read() & HENVCFG_STCE) ? MIP_VSTIP : 0); + state->mip->backdoor_write_with_mask(mask, mip_val); } } @@ -1537,7 +1538,8 @@ stimecmp_csr_t::stimecmp_csr_t(processor_t* const proc, const reg_t addr, const } bool stimecmp_csr_t::unlogged_write(const reg_t val) noexcept { - state->mip->backdoor_write_with_mask(intr_mask, state->time->read() >= val ? intr_mask : 0); + const reg_t mask = ((state->menvcfg->read() & MENVCFG_STCE) ? MIP_STIP : 0) | ((state->henvcfg->read() & HENVCFG_STCE) ? MIP_VSTIP : 0); + state->mip->backdoor_write_with_mask(mask, state->time->read() >= val ? intr_mask : 0); return basic_csr_t::unlogged_write(val); } |