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| author | Ming-Yi Lai <ming-yi.lai@mediatek.com> | 2024-01-10 14:22:58 +0800 |
|---|---|---|
| committer | Ming-Yi Lai <ming-yi.lai@mediatek.com> | 2024-03-06 17:21:01 +0800 |
| commit | 677e030594aa51ea8d6304d24b7da2ecd7006fe8 (patch) | |
| tree | 1ef9eb219ecf2f00454ce105fd1b0e107231f5a5 /riscv/csrs.cc | |
| parent | 7b5eba94285f1d12e8268899d3276bd0ff21d9c4 (diff) | |
| download | riscv-isa-sim-677e030594aa51ea8d6304d24b7da2ecd7006fe8.zip riscv-isa-sim-677e030594aa51ea8d6304d24b7da2ecd7006fe8.tar.gz riscv-isa-sim-677e030594aa51ea8d6304d24b7da2ecd7006fe8.tar.bz2 | |
Zicfilp: Support delegating software check exception handling
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 728d671..b1f4b7d 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -906,6 +906,7 @@ bool medeleg_csr_t::unlogged_write(const reg_t val) noexcept { | (1 << CAUSE_LOAD_PAGE_FAULT) | (1 << CAUSE_STORE_PAGE_FAULT) | (proc->extension_enabled('H') ? hypervisor_exceptions : 0) + | (proc->extension_enabled(EXT_ZICFILP) ? (1 << CAUSE_SOFTWARE_CHECK_FAULT) : 0) ; return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask)); } |