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| author | Andrew Waterman <andrew@sifive.com> | 2024-07-17 17:40:50 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-07-17 17:40:50 -0700 |
| commit | 34601fc48851e49f7ecbbd87405b8b7afcc4e59b (patch) | |
| tree | e72adf89369bed2adb8d84bd74c3db05283c01cd /riscv/csrs.cc | |
| parent | c0281a17d6473137c243ebd093711adb95024e68 (diff) | |
| parent | 229b159465bf23b20cc29879d0c68acc8fc792f6 (diff) | |
| download | riscv-isa-sim-master.zip riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 | |
Fix ePMP checking on hlvx instructions
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 2bb255d..068c640 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -197,13 +197,13 @@ bool pmpaddr_csr_t::access_ok(access_type type, reg_t mode, bool hlvx) const noe if (mseccfg_mml) { if (cfgx && cfgw && cfgr && cfgl) { // Locked Shared data region: Read only on both M and S/U mode. - return typer; + return typer && !hlvx; } else { const bool mml_shared_region = !cfgr && cfgw; const bool mml_chk_normal = (prvm == cfgl) && normal_rwx; const bool mml_chk_shared = - (!cfgl && cfgx && (typer || typew)) || - (!cfgl && !cfgx && (typer || (typew && prvm))) || + (!cfgl && cfgx && ((typer && !hlvx) || typew)) || + (!cfgl && !cfgx && ((typer && !hlvx) || (typew && prvm))) || (cfgl && typex) || (cfgl && typer && cfgx && prvm); return mml_shared_region ? mml_chk_shared : mml_chk_normal; |