1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
|
// See LICENSE for license details.
// For std::any_of
#include <algorithm>
#include "csrs.h"
// For processor_t:
#include "processor.h"
#include "mmu.h"
// For get_field():
#include "decode_macros.h"
// For trap_virtual_instruction and trap_illegal_instruction:
#include "trap.h"
// For require():
#include "insn_macros.h"
// For CSR_DCSR_V:
#include "debug_defines.h"
// STATE macro used by require_privilege() macro:
#undef STATE
#define STATE (*state)
// implement class csr_t
csr_t::csr_t(processor_t* const proc, const reg_t addr):
proc(proc),
state(proc->get_state()),
address(addr),
csr_priv(get_field(addr, 0x300)),
csr_read_only(get_field(addr, 0xC00) == 3) {
}
void csr_t::verify_permissions(insn_t insn, bool write) const {
// Check permissions. Raise virtual-instruction exception if V=1,
// privileges are insufficient, and the CSR belongs to supervisor or
// hypervisor. Raise illegal-instruction exception otherwise.
unsigned priv = state->prv == PRV_S && !state->v ? PRV_HS : state->prv;
if ((csr_priv == PRV_S && !proc->extension_enabled('S')) ||
(csr_priv == PRV_HS && !proc->extension_enabled('H')))
throw trap_illegal_instruction(insn.bits());
if (write && csr_read_only)
throw trap_illegal_instruction(insn.bits());
if (priv < csr_priv) {
if (state->v && csr_priv <= PRV_HS)
throw trap_virtual_instruction(insn.bits());
throw trap_illegal_instruction(insn.bits());
}
}
csr_t::~csr_t() {
}
void csr_t::write(const reg_t val) noexcept {
const bool success = unlogged_write(val);
if (success) {
log_write();
}
}
void csr_t::log_write() const noexcept {
log_special_write(address, written_value());
}
void csr_t::log_special_write(const reg_t UNUSED address, const reg_t UNUSED val) const noexcept {
if (proc->get_log_commits_enabled())
proc->get_state()->log_reg_write[((address) << 4) | 4] = {val, 0};
}
reg_t csr_t::written_value() const noexcept {
return read();
}
// implement class basic_csr_t
basic_csr_t::basic_csr_t(processor_t* const proc, const reg_t addr, const reg_t init):
csr_t(proc, addr),
val(init) {
}
bool basic_csr_t::unlogged_write(const reg_t val) noexcept {
this->val = val;
return true;
}
// implement class pmpaddr_csr_t
pmpaddr_csr_t::pmpaddr_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr),
val(0),
cfg(0),
pmpidx(address - CSR_PMPADDR0) {
}
void pmpaddr_csr_t::verify_permissions(insn_t insn, bool write) const {
csr_t::verify_permissions(insn, write);
// If n_pmp is zero, that means pmp is not implemented hence raise
// trap if it tries to access the csr. I would prefer to implement
// this by not instantiating any pmpaddr_csr_t for these regs, but
// n_pmp can change after reset() is run.
if (proc->n_pmp == 0)
throw trap_illegal_instruction(insn.bits());
}
reg_t pmpaddr_csr_t::read() const noexcept {
if ((cfg & PMP_A) >= PMP_NAPOT)
return val | (~proc->pmp_tor_mask() >> 1);
return val & proc->pmp_tor_mask();
}
bool pmpaddr_csr_t::unlogged_write(const reg_t val) noexcept {
// If no PMPs are configured, disallow access to all. Otherwise,
// allow access to all, but unimplemented ones are hardwired to
// zero. Note that n_pmp can change after reset(); otherwise I would
// implement this in state_t::reset() by instantiating the correct
// number of pmpaddr_csr_t.
if (proc->n_pmp == 0)
return false;
const bool lock_bypass = state->mseccfg->get_rlb();
const bool locked = !lock_bypass && (cfg & PMP_L);
if (pmpidx < proc->n_pmp && !locked && !next_locked_and_tor()) {
this->val = val & ((reg_t(1) << (MAX_PADDR_BITS - PMP_SHIFT)) - 1);
}
else
return false;
proc->get_mmu()->flush_tlb();
return true;
}
bool pmpaddr_csr_t::next_locked_and_tor() const noexcept {
if (pmpidx+1 >= state->max_pmp) return false; // this is the last entry
const bool lock_bypass = state->mseccfg->get_rlb();
const bool next_locked = !lock_bypass && (state->pmpaddr[pmpidx+1]->cfg & PMP_L);
const bool next_tor = (state->pmpaddr[pmpidx+1]->cfg & PMP_A) == PMP_TOR;
return next_locked && next_tor;
}
reg_t pmpaddr_csr_t::tor_paddr() const noexcept {
return (val & proc->pmp_tor_mask()) << PMP_SHIFT;
}
reg_t pmpaddr_csr_t::tor_base_paddr() const noexcept {
if (pmpidx == 0) return 0; // entry 0 always uses 0 as base
return state->pmpaddr[pmpidx-1]->tor_paddr();
}
reg_t pmpaddr_csr_t::napot_mask() const noexcept {
bool is_na4 = (cfg & PMP_A) == PMP_NA4;
reg_t mask = (val << 1) | (!is_na4) | ~proc->pmp_tor_mask();
return ~(mask & ~(mask + 1)) << PMP_SHIFT;
}
bool pmpaddr_csr_t::match4(reg_t addr) const noexcept {
if ((cfg & PMP_A) == 0) return false;
bool is_tor = (cfg & PMP_A) == PMP_TOR;
if (is_tor) return tor_base_paddr() <= addr && addr < tor_paddr();
// NAPOT or NA4:
return ((addr ^ tor_paddr()) & napot_mask()) == 0;
}
bool pmpaddr_csr_t::subset_match(reg_t addr, reg_t len) const noexcept {
if ((addr | len) & (len - 1))
abort();
reg_t base = tor_base_paddr();
reg_t tor = tor_paddr();
if ((cfg & PMP_A) == 0) return false;
bool is_tor = (cfg & PMP_A) == PMP_TOR;
bool begins_after_lower = addr >= base;
bool begins_after_upper = addr >= tor;
bool ends_before_lower = (addr & -len) < (base & -len);
bool ends_before_upper = (addr & -len) < (tor & -len);
bool tor_homogeneous = ends_before_lower || begins_after_upper ||
(begins_after_lower && ends_before_upper);
bool mask_homogeneous = ~(napot_mask() << 1) & len;
bool napot_homogeneous = mask_homogeneous || ((addr ^ tor) / len) != 0;
return !(is_tor ? tor_homogeneous : napot_homogeneous);
}
bool pmpaddr_csr_t::access_ok(access_type type, reg_t mode, bool hlvx) const noexcept {
const bool cfgx = cfg & PMP_X;
const bool cfgw = cfg & PMP_W;
const bool cfgr = cfg & PMP_R;
const bool cfgl = cfg & PMP_L;
const bool prvm = mode == PRV_M;
const bool typer = type == LOAD;
const bool typex = type == FETCH;
const bool typew = type == STORE;
const bool normal_rwx = (typer && cfgr && (!hlvx || cfgx)) || (typew && cfgw) || (typex && cfgx);
const bool mseccfg_mml = state->mseccfg->get_mml();
if (mseccfg_mml) {
if (cfgx && cfgw && cfgr && cfgl) {
// Locked Shared data region: Read only on both M and S/U mode.
return typer && !hlvx;
} else {
const bool mml_shared_region = !cfgr && cfgw;
const bool mml_chk_normal = (prvm == cfgl) && normal_rwx;
const bool mml_chk_shared =
(!cfgl && cfgx && ((typer && !hlvx) || typew)) ||
(!cfgl && !cfgx && ((typer && !hlvx) || (typew && prvm))) ||
(cfgl && typex) ||
(cfgl && typer && cfgx && prvm);
return mml_shared_region ? mml_chk_shared : mml_chk_normal;
}
} else {
const bool m_bypass = (prvm && !cfgl);
return m_bypass || normal_rwx;
}
}
// implement class pmpcfg_csr_t
pmpcfg_csr_t::pmpcfg_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr) {
}
void pmpcfg_csr_t::verify_permissions(insn_t insn, bool write) const {
csr_t::verify_permissions(insn, write);
// If n_pmp is zero, that means pmp is not implemented hence raise
// trap if it tries to access the csr. I would prefer to implement
// this by not instantiating any pmpcfg_csr_t for these regs, but
// n_pmp can change after reset() is run.
if (proc->n_pmp == 0)
throw trap_illegal_instruction(insn.bits());
}
reg_t pmpcfg_csr_t::read() const noexcept {
reg_t cfg_res = 0;
for (size_t i0 = (address - CSR_PMPCFG0) * 4, i = i0; i < i0 + proc->get_xlen() / 8 && i < state->max_pmp; i++)
cfg_res |= reg_t(state->pmpaddr[i]->cfg) << (8 * (i - i0));
return cfg_res;
}
bool pmpcfg_csr_t::unlogged_write(const reg_t val) noexcept {
if (proc->n_pmp == 0)
return false;
bool write_success = false;
const bool rlb = state->mseccfg->get_rlb();
const bool mml = state->mseccfg->get_mml();
for (size_t i0 = (address - CSR_PMPCFG0) * 4, i = i0; i < i0 + proc->get_xlen() / 8; i++) {
if (i < proc->n_pmp) {
const bool locked = (state->pmpaddr[i]->cfg & PMP_L);
if (rlb || !locked) {
uint8_t cfg = (val >> (8 * (i - i0))) & (PMP_R | PMP_W | PMP_X | PMP_A | PMP_L);
// Drop R=0 W=1 when MML = 0
// Remove the restriction when MML = 1
if (!mml) {
cfg &= ~PMP_W | ((cfg & PMP_R) ? PMP_W : 0);
}
// Disallow A=NA4 when granularity > 4
if (proc->lg_pmp_granularity != PMP_SHIFT && (cfg & PMP_A) == PMP_NA4)
cfg |= PMP_NAPOT;
/*
* Adding a rule with executable privileges that either is M-mode-only or a locked Shared-Region
* is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged.
* This restriction can be temporarily lifted e.g. during the boot process, by setting mseccfg.RLB.
*/
const bool cfgx = cfg & PMP_X;
const bool cfgw = cfg & PMP_W;
const bool cfgr = cfg & PMP_R;
if (rlb || !(mml && ((cfg & PMP_L) // M-mode-only or a locked Shared-Region
&& !(cfgx && cfgw && cfgr) // RWX = 111 is allowed
&& (cfgx || (cfgw && !cfgr)) // X=1 or RW=01 is not allowed
))) {
state->pmpaddr[i]->cfg = cfg;
}
}
write_success = true;
}
}
proc->get_mmu()->flush_tlb();
return write_success;
}
// implement class mseccfg_csr_t
mseccfg_csr_t::mseccfg_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0) {
}
void mseccfg_csr_t::verify_permissions(insn_t insn, bool write) const {
basic_csr_t::verify_permissions(insn, write);
if (!proc->extension_enabled(EXT_SMEPMP) &&
!proc->extension_enabled(EXT_SMMPM) &&
!proc->extension_enabled(EXT_ZICFILP) &&
!proc->extension_enabled(EXT_ZKR))
throw trap_illegal_instruction(insn.bits());
}
bool mseccfg_csr_t::get_mml() const noexcept {
return (read() & MSECCFG_MML);
}
bool mseccfg_csr_t::get_mmwp() const noexcept {
return (read() & MSECCFG_MMWP);
}
bool mseccfg_csr_t::get_rlb() const noexcept {
return (read() & MSECCFG_RLB);
}
bool mseccfg_csr_t::get_useed() const noexcept {
return (read() & MSECCFG_USEED);
}
bool mseccfg_csr_t::get_sseed() const noexcept {
return (read() & MSECCFG_SSEED);
}
bool mseccfg_csr_t::unlogged_write(const reg_t val) noexcept {
if (proc->n_pmp == 0)
return false;
// pmpcfg.L is 1 in any rule or entry (including disabled entries)
const bool pmplock_recorded = std::any_of(state->pmpaddr, state->pmpaddr + proc->n_pmp,
[](const pmpaddr_csr_t_p & c) { return c->is_locked(); } );
reg_t new_val = read();
// When RLB is 0 and pmplock_recorded, RLB is locked to 0.
// Otherwise set the RLB bit according val
if (!(pmplock_recorded && (read() & MSECCFG_RLB) == 0)) {
new_val &= ~MSECCFG_RLB;
new_val |= (val & MSECCFG_RLB);
}
new_val |= (val & MSECCFG_MMWP); //MMWP is sticky
new_val |= (val & MSECCFG_MML); //MML is sticky
if (proc->extension_enabled(EXT_ZKR)) {
uint64_t mask = MSECCFG_USEED | MSECCFG_SSEED;
new_val = (new_val & ~mask) | (val & mask);
}
proc->get_mmu()->flush_tlb();
if (proc->extension_enabled(EXT_ZICFILP)) {
new_val &= ~MSECCFG_MLPE;
new_val |= (val & MSECCFG_MLPE);
}
if (proc->extension_enabled(EXT_SMMPM)) {
const reg_t pmm_reserved = 1; // Reserved value of mseccfg.PMM
reg_t pmm = get_field(val, MSECCFG_PMM);
new_val = set_field(new_val, MSECCFG_PMM, pmm != pmm_reserved ? pmm : 0);
}
return basic_csr_t::unlogged_write(new_val);
}
// implement class virtualized_csr_t
virtualized_csr_t::virtualized_csr_t(processor_t* const proc, csr_t_p orig, csr_t_p virt):
csr_t(proc, orig->address),
orig_csr(orig),
virt_csr(virt) {
}
reg_t virtualized_csr_t::read() const noexcept {
return readvirt(state->v);
}
reg_t virtualized_csr_t::readvirt(bool virt) const noexcept {
return virt ? virt_csr->read() : orig_csr->read();
}
bool virtualized_csr_t::unlogged_write(const reg_t val) noexcept {
if (state->v)
virt_csr->write(val);
else
orig_csr->write(val);
return false; // virt_csr or orig_csr has already logged
}
// implement class epc_csr_t
epc_csr_t::epc_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr),
val(0) {
}
reg_t epc_csr_t::read() const noexcept {
return val & proc->pc_alignment_mask();
}
bool epc_csr_t::unlogged_write(const reg_t val) noexcept {
this->val = val & ~(reg_t)1;
return true;
}
// implement class tvec_csr_t
tvec_csr_t::tvec_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr),
val(0) {
}
reg_t tvec_csr_t::read() const noexcept {
return val;
}
bool tvec_csr_t::unlogged_write(const reg_t val) noexcept {
this->val = val & ~(reg_t)2;
return true;
}
// implement class cause_csr_t
cause_csr_t::cause_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0) {
}
reg_t cause_csr_t::read() const noexcept {
reg_t val = basic_csr_t::read();
// When reading, the interrupt bit needs to adjust to xlen. Spike does
// not generally support dynamic xlen, but this code was (partly)
// there since at least 2015 (ea58df8 and c4350ef).
if (proc->get_isa().get_max_xlen() > proc->get_xlen()) // Move interrupt bit to top of xlen
return val | ((val >> (proc->get_isa().get_max_xlen()-1)) << (proc->get_xlen()-1));
return val;
}
// implement class base_status_csr_t
base_status_csr_t::base_status_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr),
has_page(proc->extension_enabled_const('S') && proc->supports_impl(IMPL_MMU)),
sstatus_write_mask(compute_sstatus_write_mask()),
sstatus_read_mask(sstatus_write_mask | SSTATUS_UBE | SSTATUS_UXL
| (proc->get_const_xlen() == 32 ? SSTATUS32_SD : SSTATUS64_SD)) {
}
reg_t base_status_csr_t::compute_sstatus_write_mask() const noexcept {
// If a configuration has FS bits, they will always be accessible no
// matter the state of misa.
const bool has_fs = (proc->extension_enabled('S') || proc->extension_enabled('F')) && !proc->extension_enabled(EXT_ZFINX);
// Implementations w/o V may still have mstatus.vs,
const bool has_vs = proc->any_vector_extensions();
return 0
| (proc->extension_enabled('S') ? (SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP) : 0)
| (has_page ? (SSTATUS_SUM | SSTATUS_MXR) : 0)
| (has_fs ? SSTATUS_FS : 0)
| (proc->any_custom_extensions() ? SSTATUS_XS : 0)
| (has_vs ? SSTATUS_VS : 0)
| (proc->extension_enabled(EXT_ZICFILP) ? SSTATUS_SPELP : 0)
| (proc->extension_enabled(EXT_SSDBLTRP) ? SSTATUS_SDT : 0)
;
}
reg_t base_status_csr_t::adjust_sd(const reg_t val) const noexcept {
// This uses get_const_xlen() instead of get_xlen() not only because
// the variable is static, so it's only called once, but also
// because the SD bit moves when XLEN changes, which means we would
// need to call adjust_sd() on every read, instead of on every
// write.
static const reg_t sd_bit = proc->get_const_xlen() == 64 ? SSTATUS64_SD : SSTATUS32_SD;
if (((val & SSTATUS_FS) == SSTATUS_FS) ||
((val & SSTATUS_VS) == SSTATUS_VS) ||
((val & SSTATUS_XS) == SSTATUS_XS)) {
return val | sd_bit;
}
return val & ~sd_bit;
}
void base_status_csr_t::maybe_flush_tlb(const reg_t newval) noexcept {
if ((newval ^ read()) &
(MSTATUS_MPP | MSTATUS_MPRV
| (has_page ? (MSTATUS_MXR | MSTATUS_SUM) : 0)
))
proc->get_mmu()->flush_tlb();
}
namespace {
int xlen_to_uxl(int xlen) {
if (xlen == 32)
return 1;
if (xlen == 64)
return 2;
abort();
}
}
// implement class vsstatus_csr_t
vsstatus_csr_t::vsstatus_csr_t(processor_t* const proc, const reg_t addr):
base_status_csr_t(proc, addr),
val(proc->get_state()->mstatus->read() & sstatus_read_mask) {
}
bool vsstatus_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t hDTE = (state->henvcfg->read() & HENVCFG_DTE);
const reg_t adj_write_mask = sstatus_write_mask & ~(hDTE ? 0 : SSTATUS_SDT);
reg_t newval = (this->val & ~adj_write_mask) | (val & adj_write_mask);
newval = (newval & SSTATUS_SDT) ? (newval & ~SSTATUS_SIE) : newval;
if (state->v) maybe_flush_tlb(newval);
this->val = adjust_sd(newval);
return true;
}
reg_t vsstatus_csr_t::read() const noexcept {
const reg_t hDTE = state->henvcfg->read() & HENVCFG_DTE;
const reg_t adj_read_mask = sstatus_read_mask & ~(hDTE ? 0 : SSTATUS_SDT);
return this->val & adj_read_mask;
}
// implement class sstatus_proxy_csr_t
sstatus_proxy_csr_t::sstatus_proxy_csr_t(processor_t* const proc, const reg_t addr, mstatus_csr_t_p mstatus):
base_status_csr_t(proc, addr),
mstatus(mstatus) {
}
bool sstatus_proxy_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t mDTE = (state->menvcfg->read() & MENVCFG_DTE);
const reg_t adj_write_mask = sstatus_write_mask & ~(mDTE ? 0 : SSTATUS_SDT);
reg_t new_mstatus = (mstatus->read() & ~adj_write_mask) | (val & adj_write_mask);
new_mstatus = (new_mstatus & SSTATUS_SDT) ? (new_mstatus & ~SSTATUS_SIE) : new_mstatus;
// On RV32 this will only log the low 32 bits, so make sure we're
// not modifying anything in the upper 32 bits.
assert((adj_write_mask & 0xffffffffU) == adj_write_mask);
mstatus->write(new_mstatus);
return false; // avoid double logging: already logged by mstatus->write()
}
reg_t sstatus_proxy_csr_t::read() const noexcept {
const reg_t mDTE = state->menvcfg->read() & MENVCFG_DTE;
const reg_t adj_read_mask = sstatus_read_mask & ~(mDTE ? 0 : SSTATUS_SDT);
return mstatus->read() & adj_read_mask;
}
// implement class mstatus_csr_t
mstatus_csr_t::mstatus_csr_t(processor_t* const proc, const reg_t addr):
base_status_csr_t(proc, addr),
val(compute_mstatus_initial_value()) {
}
bool mstatus_csr_t::unlogged_write(const reg_t val) noexcept {
const bool has_mpv = proc->extension_enabled('H');
const bool has_gva = has_mpv;
const reg_t mask = sstatus_write_mask
| MSTATUS_MIE | MSTATUS_MPIE
| (proc->extension_enabled('U') ? MSTATUS_MPRV : 0)
| MSTATUS_MPP | MSTATUS_TW
| (proc->extension_enabled('S') ? MSTATUS_TSR : 0)
| (has_page ? MSTATUS_TVM : 0)
| (has_gva ? MSTATUS_GVA : 0)
| (has_mpv ? MSTATUS_MPV : 0)
| (proc->extension_enabled(EXT_ZICFILP) ? (MSTATUS_SPELP | MSTATUS_MPELP) : 0)
| (proc->extension_enabled(EXT_SSDBLTRP) ? SSTATUS_SDT : 0)
;
const reg_t requested_mpp = proc->legalize_privilege(get_field(val, MSTATUS_MPP));
const reg_t adjusted_val = set_field(val, MSTATUS_MPP, requested_mpp);
const reg_t new_mstatus = (read() & ~mask) | (adjusted_val & mask);
maybe_flush_tlb(new_mstatus);
this->val = adjust_sd(new_mstatus);
return true;
}
reg_t mstatus_csr_t::compute_mstatus_initial_value() const noexcept {
const reg_t big_endian_bits = (proc->extension_enabled_const('U') ? MSTATUS_UBE : 0)
| (proc->extension_enabled_const('S') ? MSTATUS_SBE : 0)
| MSTATUS_MBE;
return 0
| set_field((reg_t)0, MSTATUS_MPP, proc->extension_enabled_const('U') ? PRV_U : PRV_M)
| (proc->extension_enabled_const('U') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_UXL, xlen_to_uxl(proc->get_const_xlen())) : 0)
| (proc->extension_enabled_const('S') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_SXL, xlen_to_uxl(proc->get_const_xlen())) : 0)
| (proc->get_mmu()->is_target_big_endian() ? big_endian_bits : 0)
| 0; // initial value for mstatus
}
// implement class mnstatus_csr_t
mnstatus_csr_t::mnstatus_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0) {
}
bool mnstatus_csr_t::unlogged_write(const reg_t val) noexcept {
// NMIE can be set but not cleared
const reg_t mask = (~read() & MNSTATUS_NMIE)
| (proc->extension_enabled('H') ? MNSTATUS_MNPV : 0)
| MNSTATUS_MNPP;
const reg_t requested_mnpp = proc->legalize_privilege(get_field(val, MNSTATUS_MNPP));
const reg_t adjusted_val = set_field(val, MNSTATUS_MNPP, requested_mnpp);
const reg_t new_mnstatus = (read() & ~mask) | (adjusted_val & mask);
return basic_csr_t::unlogged_write(new_mnstatus);
}
// implement class rv32_low_csr_t
rv32_low_csr_t::rv32_low_csr_t(processor_t* const proc, const reg_t addr, csr_t_p orig):
csr_t(proc, addr),
orig(orig) {
}
reg_t rv32_low_csr_t::read() const noexcept {
return orig->read() & 0xffffffffU;
}
void rv32_low_csr_t::verify_permissions(insn_t insn, bool write) const {
orig->verify_permissions(insn, write);
}
bool rv32_low_csr_t::unlogged_write(const reg_t val) noexcept {
return orig->unlogged_write((orig->written_value() >> 32 << 32) | (val & 0xffffffffU));
}
reg_t rv32_low_csr_t::written_value() const noexcept {
return orig->written_value() & 0xffffffffU;
}
// implement class rv32_high_csr_t
rv32_high_csr_t::rv32_high_csr_t(processor_t* const proc, const reg_t addr, csr_t_p orig):
csr_t(proc, addr),
orig(orig) {
}
reg_t rv32_high_csr_t::read() const noexcept {
return (orig->read() >> 32) & 0xffffffffU;
}
void rv32_high_csr_t::verify_permissions(insn_t insn, bool write) const {
orig->verify_permissions(insn, write);
}
bool rv32_high_csr_t::unlogged_write(const reg_t val) noexcept {
return orig->unlogged_write((orig->written_value() << 32 >> 32) | ((val & 0xffffffffU) << 32));
}
reg_t rv32_high_csr_t::written_value() const noexcept {
return (orig->written_value() >> 32) & 0xffffffffU;
}
// implement class sstatus_csr_t
sstatus_csr_t::sstatus_csr_t(processor_t* const proc, sstatus_proxy_csr_t_p orig, vsstatus_csr_t_p virt):
virtualized_csr_t(proc, orig, virt),
orig_sstatus(orig),
virt_sstatus(virt) {
}
void sstatus_csr_t::dirty(const reg_t dirties) {
// As an optimization, return early if already dirty.
if ((orig_sstatus->read() & dirties) == dirties) {
if (likely(!state->v || (virt_sstatus->read() & dirties) == dirties))
return;
}
// Catch problems like #823 where P-extension instructions were not
// checking for mstatus.VS!=Off:
if (!enabled(dirties)) abort();
orig_sstatus->write(orig_sstatus->read() | dirties);
if (state->v) {
virt_sstatus->write(virt_sstatus->read() | dirties);
}
}
bool sstatus_csr_t::enabled(const reg_t which) {
if ((orig_sstatus->read() & which) != 0) {
if (!state->v || (virt_sstatus->read() & which) != 0)
return true;
}
return false;
}
// implement class misa_csr_t
misa_csr_t::misa_csr_t(processor_t* const proc, const reg_t addr, const reg_t max_isa):
basic_csr_t(proc, addr, max_isa),
max_isa(max_isa),
write_mask(max_isa & (0 // allow MABFDQCHV bits in MISA to be modified
| (1L << ('M' - 'A'))
| (1L << ('A' - 'A'))
| (1L << ('B' - 'A'))
| (1L << ('F' - 'A'))
| (1L << ('D' - 'A'))
| (1L << ('Q' - 'A'))
| (1L << ('C' - 'A'))
| (1L << ('H' - 'A'))
| (1L << ('V' - 'A'))
)
) {
}
reg_t misa_csr_t::dependency(const reg_t val, const char feature, const char depends_on) const noexcept {
return (val & (1L << (depends_on - 'A'))) ? val : (val & ~(1L << (feature - 'A')));
}
bool misa_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t old_misa = read();
// the write is ignored if increasing IALIGN would misalign the PC
if (!(val & (1L << ('C' - 'A'))) && (old_misa & (1L << ('C' - 'A'))) && (state->pc & 2))
return false;
reg_t adjusted_val = val;
adjusted_val = dependency(adjusted_val, 'D', 'F');
adjusted_val = dependency(adjusted_val, 'Q', 'D');
adjusted_val = dependency(adjusted_val, 'V', 'D');
const bool prev_h = old_misa & (1L << ('H' - 'A'));
const reg_t new_misa = (adjusted_val & write_mask) | (old_misa & ~write_mask);
const bool new_h = new_misa & (1L << ('H' - 'A'));
proc->set_extension_enable(EXT_ZCA, (new_misa & (1L << ('C' - 'A'))) || !proc->get_isa().extension_enabled('C'));
proc->set_extension_enable(EXT_ZCF, (new_misa & (1L << ('F' - 'A'))) && proc->extension_enabled(EXT_ZCA));
proc->set_extension_enable(EXT_ZCD, (new_misa & (1L << ('D' - 'A'))) && proc->extension_enabled(EXT_ZCA));
proc->set_extension_enable(EXT_ZCB, proc->extension_enabled(EXT_ZCA));
proc->set_extension_enable(EXT_ZCMP, proc->extension_enabled(EXT_ZCA));
proc->set_extension_enable(EXT_ZCMT, proc->extension_enabled(EXT_ZCA));
proc->set_extension_enable(EXT_ZFH, new_misa & (1L << ('F' - 'A')));
proc->set_extension_enable(EXT_ZFHMIN, new_misa & (1L << ('F' - 'A')));
proc->set_extension_enable(EXT_ZVFH, (new_misa & (1L << ('V' - 'A'))) && proc->extension_enabled(EXT_ZFHMIN));
proc->set_extension_enable(EXT_ZVFHMIN, new_misa & (1L << ('V' - 'A')));
proc->set_extension_enable(EXT_ZAAMO, (new_misa & (1L << ('A' - 'A'))) || !proc->get_isa().extension_enabled('A'));
proc->set_extension_enable(EXT_ZALRSC, (new_misa & (1L << ('A' - 'A'))) || !proc->get_isa().extension_enabled('A'));
proc->set_extension_enable(EXT_ZBA, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B'));
proc->set_extension_enable(EXT_ZBB, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B'));
proc->set_extension_enable(EXT_ZBS, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B'));
// update the hypervisor-only bits in MEDELEG and other CSRs
if (!new_h && prev_h) {
reg_t hypervisor_exceptions = 0
| (1 << CAUSE_VIRTUAL_SUPERVISOR_ECALL)
| (1 << CAUSE_FETCH_GUEST_PAGE_FAULT)
| (1 << CAUSE_LOAD_GUEST_PAGE_FAULT)
| (1 << CAUSE_VIRTUAL_INSTRUCTION)
| (1 << CAUSE_STORE_GUEST_PAGE_FAULT)
;
state->medeleg->write(state->medeleg->read() & ~hypervisor_exceptions);
if (state->mnstatus) state->mnstatus->write(state->mnstatus->read() & ~MNSTATUS_MNPV);
const reg_t new_mstatus = state->mstatus->read() & ~(MSTATUS_GVA | MSTATUS_MPV);
state->mstatus->write(new_mstatus);
if (state->mstatush) state->mstatush->write(new_mstatus >> 32); // log mstatush change
state->mie->write_with_mask(MIP_HS_MASK, 0); // also takes care of hie, sie
state->mip->write_with_mask(MIP_HS_MASK, 0); // also takes care of hip, sip, hvip
state->hstatus->write(0);
for (reg_t i = 0; i < N_HPMCOUNTERS; ++i) {
const reg_t new_mevent = state->mevent[i]->read() & ~(MHPMEVENT_VUINH | MHPMEVENT_VSINH);
state->mevent[i]->write(new_mevent);
}
}
return basic_csr_t::unlogged_write(new_misa);
}
bool misa_csr_t::extension_enabled_const(unsigned char ext) const noexcept {
assert(!(1 & (write_mask >> (ext - 'A'))));
return extension_enabled(ext);
}
// implement class mip_or_mie_csr_t
mip_or_mie_csr_t::mip_or_mie_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr),
val(0) {
}
reg_t mip_or_mie_csr_t::read() const noexcept {
return val;
}
void mip_or_mie_csr_t::write_with_mask(const reg_t mask, const reg_t val) noexcept {
this->val = (this->val & ~mask) | (val & mask);
log_write();
}
bool mip_or_mie_csr_t::unlogged_write(const reg_t val) noexcept {
write_with_mask(write_mask(), val);
return false; // avoid double logging: already logged by write_with_mask()
}
mip_csr_t::mip_csr_t(processor_t* const proc, const reg_t addr):
mip_or_mie_csr_t(proc, addr) {
}
reg_t mip_csr_t::read() const noexcept {
return val | state->hvip->basic_csr_t::read();
}
void mip_csr_t::backdoor_write_with_mask(const reg_t mask, const reg_t val) noexcept {
this->val = (this->val & ~mask) | (val & mask);
}
reg_t mip_csr_t::write_mask() const noexcept {
// MIP_STIP is writable unless SSTC exists and STCE is set in MENVCFG
const reg_t supervisor_ints = proc->extension_enabled('S') ? MIP_SSIP | ((state->menvcfg->read() & MENVCFG_STCE) ? 0 : MIP_STIP) | MIP_SEIP : 0;
const reg_t lscof_int = proc->extension_enabled(EXT_SSCOFPMF) ? MIP_LCOFIP : 0;
const reg_t vssip_int = proc->extension_enabled('H') ? MIP_VSSIP : 0;
const reg_t hypervisor_ints = proc->extension_enabled('H') ? MIP_HS_MASK : 0;
// We must mask off sgeip, vstip, and vseip. All three of these
// bits are aliases for the same bits in hip. The hip spec says:
// * sgeip is read-only -- write hgeip instead
// * vseip is read-only -- write hvip instead
// * vstip is read-only -- write hvip instead
return (supervisor_ints | hypervisor_ints | lscof_int) &
(MIP_SEIP | MIP_SSIP | MIP_STIP | MIP_LCOFIP | vssip_int);
}
mie_csr_t::mie_csr_t(processor_t* const proc, const reg_t addr):
mip_or_mie_csr_t(proc, addr) {
}
reg_t mie_csr_t::write_mask() const noexcept {
const reg_t supervisor_ints = proc->extension_enabled('S') ? MIP_SSIP | MIP_STIP | MIP_SEIP : 0;
const reg_t lscof_int = proc->extension_enabled(EXT_SSCOFPMF) ? MIP_LCOFIP : 0;
const reg_t hypervisor_ints = proc->extension_enabled('H') ? MIP_HS_MASK : 0;
const reg_t coprocessor_ints = (reg_t)proc->any_custom_extensions() << IRQ_COP;
const reg_t delegable_ints = supervisor_ints | coprocessor_ints | lscof_int;
const reg_t all_ints = delegable_ints | hypervisor_ints | MIP_MSIP | MIP_MTIP | MIP_MEIP;
return all_ints;
}
// implement class generic_int_accessor_t
generic_int_accessor_t::generic_int_accessor_t(state_t* const state,
const reg_t read_mask,
const reg_t ip_write_mask,
const reg_t ie_write_mask,
const mask_mode_t mask_mode,
const int shiftamt):
state(state),
read_mask(read_mask),
ip_write_mask(ip_write_mask),
ie_write_mask(ie_write_mask),
mask_mideleg(mask_mode == MIDELEG),
mask_hideleg(mask_mode == HIDELEG),
shiftamt(shiftamt) {
}
reg_t generic_int_accessor_t::ip_read() const noexcept {
return (state->mip->read() & deleg_mask() & read_mask) >> shiftamt;
}
void generic_int_accessor_t::ip_write(const reg_t val) noexcept {
const reg_t mask = deleg_mask() & ip_write_mask;
state->mip->write_with_mask(mask, val << shiftamt);
}
reg_t generic_int_accessor_t::ie_read() const noexcept {
return (state->mie->read() & deleg_mask() & read_mask) >> shiftamt;
}
void generic_int_accessor_t::ie_write(const reg_t val) noexcept {
const reg_t mask = deleg_mask() & ie_write_mask;
state->mie->write_with_mask(mask, val << shiftamt);
}
reg_t generic_int_accessor_t::deleg_mask() const {
const reg_t hideleg_mask = mask_hideleg ? state->hideleg->read() : (reg_t)~0;
const reg_t mideleg_mask = mask_mideleg ? state->mideleg->read() : (reg_t)~0;
return hideleg_mask & mideleg_mask;
}
// implement class mip_proxy_csr_t
mip_proxy_csr_t::mip_proxy_csr_t(processor_t* const proc, const reg_t addr, generic_int_accessor_t_p accr):
csr_t(proc, addr),
accr(accr) {
}
reg_t mip_proxy_csr_t::read() const noexcept {
return accr->ip_read();
}
bool mip_proxy_csr_t::unlogged_write(const reg_t val) noexcept {
accr->ip_write(val);
return false; // accr has already logged
}
// implement class mie_proxy_csr_t
mie_proxy_csr_t::mie_proxy_csr_t(processor_t* const proc, const reg_t addr, generic_int_accessor_t_p accr):
csr_t(proc, addr),
accr(accr) {
}
reg_t mie_proxy_csr_t::read() const noexcept {
return accr->ie_read();
}
bool mie_proxy_csr_t::unlogged_write(const reg_t val) noexcept {
accr->ie_write(val);
return false; // accr has already logged
}
// implement class mideleg_csr_t
mideleg_csr_t::mideleg_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0) {
}
reg_t mideleg_csr_t::read() const noexcept {
reg_t val = basic_csr_t::read();
if (proc->extension_enabled('H')) return val | MIDELEG_FORCED_MASK;
// No need to clear MIDELEG_FORCED_MASK because those bits can never
// get set in val.
return val;
}
void mideleg_csr_t::verify_permissions(insn_t insn, bool write) const {
basic_csr_t::verify_permissions(insn, write);
if (!proc->extension_enabled('S'))
throw trap_illegal_instruction(insn.bits());
}
bool mideleg_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t supervisor_ints = proc->extension_enabled('S') ? MIP_SSIP | MIP_STIP | MIP_SEIP : 0;
const reg_t lscof_int = proc->extension_enabled(EXT_SSCOFPMF) ? MIP_LCOFIP : 0;
const reg_t coprocessor_ints = (reg_t)proc->any_custom_extensions() << IRQ_COP;
const reg_t delegable_ints = supervisor_ints | coprocessor_ints | lscof_int;
return basic_csr_t::unlogged_write(val & delegable_ints);
}
// implement class medeleg_csr_t
medeleg_csr_t::medeleg_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0),
hypervisor_exceptions(0
| (1 << CAUSE_VIRTUAL_SUPERVISOR_ECALL)
| (1 << CAUSE_FETCH_GUEST_PAGE_FAULT)
| (1 << CAUSE_LOAD_GUEST_PAGE_FAULT)
| (1 << CAUSE_VIRTUAL_INSTRUCTION)
| (1 << CAUSE_STORE_GUEST_PAGE_FAULT)
) {
}
void medeleg_csr_t::verify_permissions(insn_t insn, bool write) const {
basic_csr_t::verify_permissions(insn, write);
if (!proc->extension_enabled('S'))
throw trap_illegal_instruction(insn.bits());
}
bool medeleg_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t mask = 0
| (1 << CAUSE_MISALIGNED_FETCH)
| (1 << CAUSE_FETCH_ACCESS)
| (1 << CAUSE_ILLEGAL_INSTRUCTION)
| (1 << CAUSE_BREAKPOINT)
| (1 << CAUSE_MISALIGNED_LOAD)
| (1 << CAUSE_LOAD_ACCESS)
| (1 << CAUSE_MISALIGNED_STORE)
| (1 << CAUSE_STORE_ACCESS)
| (1 << CAUSE_USER_ECALL)
| (1 << CAUSE_SUPERVISOR_ECALL)
| (1 << CAUSE_FETCH_PAGE_FAULT)
| (1 << CAUSE_LOAD_PAGE_FAULT)
| (1 << CAUSE_STORE_PAGE_FAULT)
| (proc->extension_enabled('H') ? hypervisor_exceptions : 0)
| (1 << CAUSE_SOFTWARE_CHECK_FAULT)
| (1 << CAUSE_HARDWARE_ERROR_FAULT)
;
return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask));
}
// implement class masked_csr_t
masked_csr_t::masked_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init):
basic_csr_t(proc, addr, init),
mask(mask) {
}
bool masked_csr_t::unlogged_write(const reg_t val) noexcept {
return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask));
}
envcfg_csr_t::envcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask,
const reg_t init):
masked_csr_t(proc, addr, mask, init) {
// In unlogged_write() we WARLize this field for all three of [msh]envcfg
assert(MENVCFG_CBIE == SENVCFG_CBIE && MENVCFG_CBIE == HENVCFG_CBIE);
}
bool envcfg_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t cbie_reserved = 2; // Reserved value of xenvcfg.CBIE
reg_t adjusted_val = get_field(val, MENVCFG_CBIE) != cbie_reserved ? val : set_field(val, MENVCFG_CBIE, 0);
const reg_t pmm_reserved = 1; // Reserved value of xseccfg.PMM
const reg_t pmm = get_field(adjusted_val, MENVCFG_PMM);
adjusted_val = set_field(adjusted_val, MENVCFG_PMM, pmm != pmm_reserved ? pmm : 0);
if (get_field(adjusted_val, MENVCFG_PMM) != get_field(read(), MENVCFG_PMM))
proc->get_mmu()->flush_tlb();
return masked_csr_t::unlogged_write(adjusted_val);
}
// implement class henvcfg_csr_t
henvcfg_csr_t::henvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init, csr_t_p menvcfg):
envcfg_csr_t(proc, addr, mask, init),
menvcfg(menvcfg) {
}
// implement class base_atp_csr_t and family
base_atp_csr_t::base_atp_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0) {
}
bool base_atp_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t newval = proc->supports_impl(IMPL_MMU) ? compute_new_satp(val) : 0;
if (newval != read())
proc->get_mmu()->flush_tlb();
return basic_csr_t::unlogged_write(newval);
}
bool base_atp_csr_t::satp_valid(reg_t val) const noexcept {
if (proc->get_xlen() == 32) {
switch (get_field(val, SATP32_MODE)) {
case SATP_MODE_SV32: return proc->supports_impl(IMPL_MMU_SV32);
case SATP_MODE_OFF: return true;
default: return false;
}
} else {
switch (get_field(val, SATP64_MODE)) {
case SATP_MODE_SV39: return proc->supports_impl(IMPL_MMU_SV39);
case SATP_MODE_SV48: return proc->supports_impl(IMPL_MMU_SV48);
case SATP_MODE_SV57: return proc->supports_impl(IMPL_MMU_SV57);
case SATP_MODE_OFF: return true;
default: return false;
}
}
}
reg_t base_atp_csr_t::compute_new_satp(reg_t val) const noexcept {
reg_t rv64_ppn_mask = (reg_t(1) << (MAX_PADDR_BITS - PGSHIFT)) - 1;
reg_t mode_mask = proc->get_xlen() == 32 ? SATP32_MODE : SATP64_MODE;
reg_t asid_mask_if_enabled = proc->get_xlen() == 32 ? SATP32_ASID : SATP64_ASID;
reg_t asid_mask = proc->supports_impl(IMPL_MMU_ASID) ? asid_mask_if_enabled : 0;
reg_t ppn_mask = proc->get_xlen() == 32 ? SATP32_PPN : SATP64_PPN & rv64_ppn_mask;
reg_t new_mask = (satp_valid(val) ? mode_mask : 0) | asid_mask | ppn_mask;
reg_t old_mask = satp_valid(val) ? 0 : mode_mask;
return (new_mask & val) | (old_mask & read());
}
satp_csr_t::satp_csr_t(processor_t* const proc, const reg_t addr):
base_atp_csr_t(proc, addr) {
}
void satp_csr_t::verify_permissions(insn_t insn, bool write) const {
base_atp_csr_t::verify_permissions(insn, write);
if (get_field(state->mstatus->read(), MSTATUS_TVM))
require(state->prv == PRV_M);
}
virtualized_satp_csr_t::virtualized_satp_csr_t(processor_t* const proc, satp_csr_t_p orig, csr_t_p virt):
virtualized_csr_t(proc, orig, virt),
orig_satp(orig) {
}
void virtualized_satp_csr_t::verify_permissions(insn_t insn, bool write) const {
virtualized_csr_t::verify_permissions(insn, write);
// If satp is accessed from VS mode, it's really accessing vsatp,
// and the hstatus.VTVM bit controls.
if (state->v) {
if (get_field(state->hstatus->read(), HSTATUS_VTVM))
throw trap_virtual_instruction(insn.bits());
}
else {
orig_csr->verify_permissions(insn, write);
}
}
bool virtualized_satp_csr_t::unlogged_write(const reg_t val) noexcept {
// If unsupported Mode field: no change to contents
const reg_t newval = orig_satp->satp_valid(val) ? val : read();
return virtualized_csr_t::unlogged_write(newval);
}
// implement class wide_counter_csr_t
wide_counter_csr_t::wide_counter_csr_t(processor_t* const proc, const reg_t addr, smcntrpmf_csr_t_p config_csr):
csr_t(proc, addr),
val(0),
config_csr(config_csr) {
}
reg_t wide_counter_csr_t::read() const noexcept {
return val;
}
void wide_counter_csr_t::bump(const reg_t howmuch) noexcept {
if (is_counting_enabled()) {
val += howmuch; // to keep log reasonable size, don't log every bump
}
// Clear cached value
config_csr->reset_prev();
}
bool wide_counter_csr_t::unlogged_write(const reg_t val) noexcept {
this->val = val;
// The ISA mandates that if an instruction writes instret, the write
// takes precedence over the increment to instret. However, Spike
// unconditionally increments instret after executing an instruction.
// Correct for this artifact by decrementing instret here.
// Ensure that Smctrpmf hasn't disabled counting.
if (is_counting_enabled()) {
this->val--;
}
return true;
}
reg_t wide_counter_csr_t::written_value() const noexcept {
// Re-adjust for upcoming bump()
return this->val + 1;
}
// Returns true if counting is not inhibited by Smcntrpmf.
// Note that minstretcfg / mcyclecfg / mhpmevent* share the same inhibit bits.
bool wide_counter_csr_t::is_counting_enabled() const noexcept {
auto prv = state->prv_changed ? state->prev_prv : state->prv;
auto v = state->v_changed ? state->prev_v : state->v;
auto mask = MHPMEVENT_MINH;
if (prv == PRV_S) {
mask = v ? MHPMEVENT_VSINH : MHPMEVENT_SINH;
} else if (prv == PRV_U) {
mask = v ? MHPMEVENT_VUINH : MHPMEVENT_UINH;
}
return (config_csr->read_prev() & mask) == 0;
}
// implement class time_counter_csr_t
time_counter_csr_t::time_counter_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr),
shadow_val(0) {
}
reg_t time_counter_csr_t::read() const noexcept {
// reading the time CSR in VS or VU mode returns the sum of the contents of
// htimedelta and the actual value of time.
if (state->v)
return shadow_val + state->htimedelta->read();
else
return shadow_val;
}
void time_counter_csr_t::sync(const reg_t val) noexcept {
shadow_val = val;
if (proc->extension_enabled(EXT_SSTC)) {
const reg_t mip_val = (shadow_val >= state->stimecmp->read() ? MIP_STIP : 0) |
(shadow_val + state->htimedelta->read() >= state->vstimecmp->read() ? MIP_VSTIP : 0);
const reg_t mask = ((state->menvcfg->read() & MENVCFG_STCE) ? MIP_STIP : 0) | ((state->henvcfg->read() & HENVCFG_STCE) ? MIP_VSTIP : 0);
state->mip->backdoor_write_with_mask(mask, mip_val);
}
}
proxy_csr_t::proxy_csr_t(processor_t* const proc, const reg_t addr, csr_t_p delegate):
csr_t(proc, addr),
delegate(delegate) {
}
reg_t proxy_csr_t::read() const noexcept {
return delegate->read();
}
bool proxy_csr_t::unlogged_write(const reg_t val) noexcept {
delegate->write(val); // log only under the original (delegate's) name
return false;
}
const_csr_t::const_csr_t(processor_t* const proc, const reg_t addr, reg_t val):
csr_t(proc, addr),
val(val) {
}
reg_t const_csr_t::read() const noexcept {
return val;
}
bool const_csr_t::unlogged_write(const reg_t UNUSED val) noexcept {
return false;
}
counter_proxy_csr_t::counter_proxy_csr_t(processor_t* const proc, const reg_t addr, csr_t_p delegate):
proxy_csr_t(proc, addr, delegate) {
}
bool counter_proxy_csr_t::myenable(csr_t_p counteren) const noexcept {
return 1 & (counteren->read() >> (address & 31));
}
void counter_proxy_csr_t::verify_permissions(insn_t insn, bool write) const {
proxy_csr_t::verify_permissions(insn, write);
const bool mctr_ok = (state->prv < PRV_M) ? myenable(state->mcounteren) : true;
const bool hctr_ok = state->v ? myenable(state->hcounteren) : true;
const bool sctr_ok = (proc->extension_enabled('S') && state->prv < PRV_S) ? myenable(state->scounteren) : true;
if (!mctr_ok)
throw trap_illegal_instruction(insn.bits());
if (!hctr_ok)
throw trap_virtual_instruction(insn.bits());
if (!sctr_ok) {
if (state->v)
throw trap_virtual_instruction(insn.bits());
else
throw trap_illegal_instruction(insn.bits());
}
}
mevent_csr_t::mevent_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0) {
}
bool mevent_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t mask = proc->extension_enabled(EXT_SSCOFPMF) ? MHPMEVENT_OF | MHPMEVENT_MINH
| (proc->extension_enabled_const('U') ? MHPMEVENT_UINH : 0)
| (proc->extension_enabled_const('S') ? MHPMEVENT_SINH : 0)
| (proc->extension_enabled('H') ? MHPMEVENT_VUINH | MHPMEVENT_VSINH : 0) : 0;
return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask));
}
hypervisor_csr_t::hypervisor_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0) {
}
void hypervisor_csr_t::verify_permissions(insn_t insn, bool write) const {
basic_csr_t::verify_permissions(insn, write);
if (!proc->extension_enabled('H'))
throw trap_illegal_instruction(insn.bits());
}
hideleg_csr_t::hideleg_csr_t(processor_t* const proc, const reg_t addr, csr_t_p mideleg):
masked_csr_t(proc, addr, MIP_VS_MASK, 0),
mideleg(mideleg) {
}
reg_t hideleg_csr_t::read() const noexcept {
return masked_csr_t::read() & mideleg->read();
};
hgatp_csr_t::hgatp_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0) {
}
void hgatp_csr_t::verify_permissions(insn_t insn, bool write) const {
basic_csr_t::verify_permissions(insn, write);
if (!state->v && get_field(state->mstatus->read(), MSTATUS_TVM))
require_privilege(PRV_M);
}
bool hgatp_csr_t::unlogged_write(const reg_t val) noexcept {
proc->get_mmu()->flush_tlb();
reg_t mask;
if (proc->get_const_xlen() == 32) {
mask = HGATP32_PPN |
HGATP32_MODE |
(proc->supports_impl(IMPL_MMU_VMID) ? HGATP32_VMID : 0);
} else {
mask = (HGATP64_PPN & ((reg_t(1) << (MAX_PADDR_BITS - PGSHIFT)) - 1)) |
(proc->supports_impl(IMPL_MMU_VMID) ? HGATP64_VMID : 0);
if (get_field(val, HGATP64_MODE) == HGATP_MODE_OFF ||
(proc->supports_impl(IMPL_MMU_SV39) && get_field(val, HGATP64_MODE) == HGATP_MODE_SV39X4) ||
(proc->supports_impl(IMPL_MMU_SV48) && get_field(val, HGATP64_MODE) == HGATP_MODE_SV48X4) ||
(proc->supports_impl(IMPL_MMU_SV57) && get_field(val, HGATP64_MODE) == HGATP_MODE_SV57X4))
mask |= HGATP64_MODE;
}
mask &= ~(reg_t)3;
return basic_csr_t::unlogged_write((read() & ~mask) | (val & mask));
}
tselect_csr_t::tselect_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0) {
}
bool tselect_csr_t::unlogged_write(const reg_t val) noexcept {
return basic_csr_t::unlogged_write((val < proc->TM.count()) ? val : read());
}
tdata1_csr_t::tdata1_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr) {
}
reg_t tdata1_csr_t::read() const noexcept {
return proc->TM.tdata1_read(state->tselect->read());
}
bool tdata1_csr_t::unlogged_write(const reg_t val) noexcept {
return proc->TM.tdata1_write(state->tselect->read(), val);
}
tdata2_csr_t::tdata2_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr) {
}
reg_t tdata2_csr_t::read() const noexcept {
return proc->TM.tdata2_read(state->tselect->read());
}
bool tdata2_csr_t::unlogged_write(const reg_t val) noexcept {
return proc->TM.tdata2_write(state->tselect->read(), val);
}
tdata3_csr_t::tdata3_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr) {
}
reg_t tdata3_csr_t::read() const noexcept {
return proc->TM.tdata3_read(state->tselect->read());
}
bool tdata3_csr_t::unlogged_write(const reg_t val) noexcept {
return proc->TM.tdata3_write(state->tselect->read(), val);
}
tinfo_csr_t::tinfo_csr_t(processor_t* const proc, const reg_t addr) :
csr_t(proc, addr) {
}
reg_t tinfo_csr_t::read() const noexcept {
return proc->TM.tinfo_read(state->tselect->read());
}
debug_mode_csr_t::debug_mode_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, 0) {
}
void debug_mode_csr_t::verify_permissions(insn_t insn, bool write) const {
basic_csr_t::verify_permissions(insn, write);
if (!state->debug_mode)
throw trap_illegal_instruction(insn.bits());
}
dpc_csr_t::dpc_csr_t(processor_t* const proc, const reg_t addr):
epc_csr_t(proc, addr) {
}
void dpc_csr_t::verify_permissions(insn_t insn, bool write) const {
epc_csr_t::verify_permissions(insn, write);
if (!state->debug_mode)
throw trap_illegal_instruction(insn.bits());
}
dcsr_csr_t::dcsr_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr),
prv(0),
step(false),
ebreakm(false),
ebreaks(false),
ebreaku(false),
ebreakvs(false),
ebreakvu(false),
halt(false),
v(false),
cause(0),
pelp(elp_t::NO_LP_EXPECTED) {
}
void dcsr_csr_t::verify_permissions(insn_t insn, bool write) const {
csr_t::verify_permissions(insn, write);
if (!state->debug_mode)
throw trap_illegal_instruction(insn.bits());
}
reg_t dcsr_csr_t::read() const noexcept {
reg_t result = 0;
result = set_field(result, DCSR_XDEBUGVER, 1);
result = set_field(result, DCSR_EBREAKM, ebreakm);
result = set_field(result, DCSR_EBREAKS, ebreaks);
result = set_field(result, DCSR_EBREAKU, ebreaku);
result = set_field(result, CSR_DCSR_EBREAKVS, ebreakvs);
result = set_field(result, CSR_DCSR_EBREAKVU, ebreakvu);
result = set_field(result, DCSR_STOPCOUNT, 0);
result = set_field(result, DCSR_STOPTIME, 0);
result = set_field(result, DCSR_CAUSE, cause);
result = set_field(result, DCSR_STEP, step);
result = set_field(result, DCSR_PRV, prv);
result = set_field(result, CSR_DCSR_V, v);
result = set_field(result, DCSR_PELP, pelp);
return result;
}
bool dcsr_csr_t::unlogged_write(const reg_t val) noexcept {
prv = get_field(val, DCSR_PRV);
step = get_field(val, DCSR_STEP);
// TODO: ndreset and fullreset
ebreakm = get_field(val, DCSR_EBREAKM);
ebreaks = proc->extension_enabled('S') ? get_field(val, DCSR_EBREAKS) : false;
ebreaku = proc->extension_enabled('U') ? get_field(val, DCSR_EBREAKU) : false;
ebreakvs = proc->extension_enabled('H') ? get_field(val, CSR_DCSR_EBREAKVS) : false;
ebreakvu = proc->extension_enabled('H') ? get_field(val, CSR_DCSR_EBREAKVU) : false;
v = proc->extension_enabled('H') ? get_field(val, CSR_DCSR_V) : false;
pelp = proc->extension_enabled(EXT_ZICFILP) ?
static_cast<elp_t>(get_field(val, DCSR_PELP)) : elp_t::NO_LP_EXPECTED;
return true;
}
void dcsr_csr_t::update_fields(const uint8_t cause, const reg_t prv,
const bool v, const elp_t pelp) noexcept {
this->cause = cause;
this->prv = prv;
this->v = v;
this->pelp = pelp;
log_write();
}
float_csr_t::float_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init):
masked_csr_t(proc, addr, mask, init) {
}
void float_csr_t::verify_permissions(insn_t insn, bool write) const {
masked_csr_t::verify_permissions(insn, write);
require_fs;
if (!proc->extension_enabled('F') && !proc->extension_enabled(EXT_ZFINX))
throw trap_illegal_instruction(insn.bits());
if (proc->extension_enabled(EXT_SMSTATEEN) && proc->extension_enabled(EXT_ZFINX)) {
if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & MSTATEEN0_FCSR))
throw trap_illegal_instruction(insn.bits());
if (state->v && !(state->hstateen[0]->read() & HSTATEEN0_FCSR))
throw trap_virtual_instruction(insn.bits());
if ((proc->extension_enabled('S') && state->prv < PRV_S) && !(state->sstateen[0]->read() & SSTATEEN0_FCSR)) {
if (state->v)
throw trap_virtual_instruction(insn.bits());
else
throw trap_illegal_instruction(insn.bits());
}
}
}
bool float_csr_t::unlogged_write(const reg_t val) noexcept {
dirty_fp_state;
return masked_csr_t::unlogged_write(val);
}
composite_csr_t::composite_csr_t(processor_t* const proc, const reg_t addr, csr_t_p upper_csr, csr_t_p lower_csr, const unsigned upper_lsb):
csr_t(proc, addr),
upper_csr(upper_csr),
lower_csr(lower_csr),
upper_lsb(upper_lsb) {
}
void composite_csr_t::verify_permissions(insn_t insn, bool write) const {
// It is reasonable to assume that either underlying CSR will have
// the same permissions as this composite.
upper_csr->verify_permissions(insn, write);
}
reg_t composite_csr_t::read() const noexcept {
return (upper_csr->read() << upper_lsb) | lower_csr->read();
}
bool composite_csr_t::unlogged_write(const reg_t val) noexcept {
upper_csr->write(val >> upper_lsb);
lower_csr->write(val);
return false; // logging is done only by the underlying CSRs
}
seed_csr_t::seed_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr) {
}
void seed_csr_t::verify_permissions(insn_t insn, bool write) const {
/* Read-only access disallowed due to wipe-on-read side effect */
/* XXX mseccfg.sseed and mseccfg.useed should be verified. */
if (!proc->extension_enabled(EXT_ZKR) || !write)
throw trap_illegal_instruction(insn.bits());
csr_t::verify_permissions(insn, write);
if (state->v) {
if (state->mseccfg->get_sseed() && write)
throw trap_virtual_instruction(insn.bits());
else
throw trap_illegal_instruction(insn.bits());
} else if ((state->prv == PRV_U && !state->mseccfg->get_useed()) ||
(state->prv == PRV_S && !state->mseccfg->get_sseed())) {
throw trap_illegal_instruction(insn.bits());
}
}
reg_t seed_csr_t::read() const noexcept {
return proc->es.get_seed();
}
bool seed_csr_t::unlogged_write(const reg_t val) noexcept {
proc->es.set_seed(val);
return true;
}
vector_csr_t::vector_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init):
basic_csr_t(proc, addr, init),
mask(mask) {
}
void vector_csr_t::verify_permissions(insn_t insn, bool write) const {
require(proc->any_vector_extensions() && STATE.sstatus->enabled(SSTATUS_VS));
basic_csr_t::verify_permissions(insn, write);
}
void vector_csr_t::write_raw(const reg_t val) noexcept {
const bool success = basic_csr_t::unlogged_write(val);
if (success)
log_write();
}
bool vector_csr_t::unlogged_write(const reg_t val) noexcept {
if (mask == 0) return false;
dirty_vs_state;
return basic_csr_t::unlogged_write(val & mask);
}
vxsat_csr_t::vxsat_csr_t(processor_t* const proc, const reg_t addr):
masked_csr_t(proc, addr, /*mask*/ 1, /*init*/ 0) {
}
void vxsat_csr_t::verify_permissions(insn_t insn, bool write) const {
require(proc->any_vector_extensions() && STATE.sstatus->enabled(SSTATUS_VS));
masked_csr_t::verify_permissions(insn, write);
}
bool vxsat_csr_t::unlogged_write(const reg_t val) noexcept {
dirty_vs_state;
return masked_csr_t::unlogged_write(val);
}
// implement class hstateen_csr_t
hstateen_csr_t::hstateen_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask,
const reg_t init, uint8_t index):
basic_csr_t(proc, addr, init),
index(index),
mask(mask) {
}
reg_t hstateen_csr_t::read() const noexcept {
// For every bit in an mstateen CSR that is zero (whether read-only zero or set to zero),
// the same bit appears as read-only zero in the matching hstateen and sstateen CSRs
return basic_csr_t::read() & state->mstateen[index]->read();
}
bool hstateen_csr_t::unlogged_write(const reg_t val) noexcept {
// For every bit in an mstateen CSR that is zero (whether read-only zero or set to zero),
// the same bit appears as read-only zero in the matching hstateen and sstateen CSRs
const reg_t mask = this->mask & state->mstateen[index]->read();
return basic_csr_t::unlogged_write((basic_csr_t::read() & ~mask) | (val & mask));
}
void hstateen_csr_t::verify_permissions(insn_t insn, bool write) const {
if ((state->prv < PRV_M) && !(state->mstateen[index]->read() & MSTATEEN_HSTATEEN))
throw trap_illegal_instruction(insn.bits());
basic_csr_t::verify_permissions(insn, write);
}
// implement class sstateen_csr_t
sstateen_csr_t::sstateen_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask,
const reg_t init, uint8_t index):
hstateen_csr_t(proc, addr, mask, init, index) {
}
reg_t sstateen_csr_t::read() const noexcept {
// For every bit in an mstateen CSR that is zero (whether read-only zero or set to zero),
// the same bit appears as read-only zero in the matching hstateen and sstateen CSRs
// For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero),
// the same bit appears as read-only zero in sstateen when accessed in VS-mode
if (state->v)
return hstateen_csr_t::read() & state->hstateen[index]->read();
else
return hstateen_csr_t::read();
}
bool sstateen_csr_t::unlogged_write(const reg_t val) noexcept {
// For every bit in an mstateen CSR that is zero (whether read-only zero or set to zero),
// the same bit appears as read-only zero in the matching hstateen and sstateen CSRs
// For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero),
// the same bit appears as read-only zero in sstateen when accessed in VS-mode
if (state->v)
return hstateen_csr_t::unlogged_write(val & state->hstateen[index]->read());
else
return hstateen_csr_t::unlogged_write(val);
}
void sstateen_csr_t::verify_permissions(insn_t insn, bool write) const {
hstateen_csr_t::verify_permissions(insn, write);
if (state->v && !(state->hstateen[index]->read() & HSTATEEN_SSTATEEN))
throw trap_virtual_instruction(insn.bits());
}
// implement class senvcfg_csr_t
senvcfg_csr_t::senvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask,
const reg_t init):
envcfg_csr_t(proc, addr, mask, init) {
}
void senvcfg_csr_t::verify_permissions(insn_t insn, bool write) const {
if (proc->extension_enabled(EXT_SMSTATEEN)) {
if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & MSTATEEN0_HENVCFG))
throw trap_illegal_instruction(insn.bits());
if (state->v && !(state->hstateen[0]->read() & HSTATEEN0_SENVCFG))
throw trap_virtual_instruction(insn.bits());
}
masked_csr_t::verify_permissions(insn, write);
}
// senvcfg.sse is read_only 0 when menvcfg.sse = 0
reg_t senvcfg_csr_t::read() const noexcept {
reg_t envcfg = state->v ? state->henvcfg->read() : state->menvcfg->read();
return masked_csr_t::read() & ~(envcfg & MENVCFG_SSE ? 0 : MENVCFG_SSE);
}
bool senvcfg_csr_t::unlogged_write(const reg_t val) noexcept {
reg_t envcfg = state->v ? state->henvcfg->read() : state->menvcfg->read();
const reg_t mask = envcfg | ~MENVCFG_SSE;
return envcfg_csr_t::unlogged_write((masked_csr_t::read() & ~mask) | (val & mask));
}
void henvcfg_csr_t::verify_permissions(insn_t insn, bool write) const {
if (proc->extension_enabled(EXT_SMSTATEEN)) {
if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & MSTATEEN0_HENVCFG))
throw trap_illegal_instruction(insn.bits());
}
masked_csr_t::verify_permissions(insn, write);
}
bool henvcfg_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t mask = menvcfg->read() | ~(MENVCFG_PBMTE | MENVCFG_STCE | MENVCFG_ADUE | MENVCFG_DTE | MENVCFG_SSE);
return envcfg_csr_t::unlogged_write((masked_csr_t::read() & ~mask) | (val & mask));
}
stimecmp_csr_t::stimecmp_csr_t(processor_t* const proc, const reg_t addr, const reg_t imask):
basic_csr_t(proc, addr, 0), intr_mask(imask) {
}
bool stimecmp_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t mask = ((state->menvcfg->read() & MENVCFG_STCE) ? MIP_STIP : 0) | ((state->henvcfg->read() & HENVCFG_STCE) ? MIP_VSTIP : 0);
state->mip->backdoor_write_with_mask(mask, state->time->read() >= val ? intr_mask : 0);
return basic_csr_t::unlogged_write(val);
}
virtualized_stimecmp_csr_t::virtualized_stimecmp_csr_t(processor_t* const proc, csr_t_p orig, csr_t_p virt):
virtualized_csr_t(proc, orig, virt) {
}
void stimecmp_csr_t::verify_permissions(insn_t insn, bool write) const {
if (!(state->menvcfg->read() & MENVCFG_STCE)) {
// access to (v)stimecmp with MENVCFG.STCE = 0
if (state->prv < PRV_M)
throw trap_illegal_instruction(insn.bits());
}
state->time_proxy->verify_permissions(insn, false);
if (state->v && !(state->henvcfg->read() & HENVCFG_STCE)) {
// access to vstimecmp with MENVCFG.STCE = 1 and HENVCFG.STCE = 0 when V = 1
throw trap_virtual_instruction(insn.bits());
}
basic_csr_t::verify_permissions(insn, write);
}
void virtualized_stimecmp_csr_t::verify_permissions(insn_t insn, bool write) const {
orig_csr->verify_permissions(insn, write);
}
scountovf_csr_t::scountovf_csr_t(processor_t* const proc, const reg_t addr):
csr_t(proc, addr) {
}
void scountovf_csr_t::verify_permissions(insn_t insn, bool write) const {
if (!proc->extension_enabled(EXT_SSCOFPMF))
throw trap_illegal_instruction(insn.bits());
csr_t::verify_permissions(insn, write);
}
reg_t scountovf_csr_t::read() const noexcept {
reg_t val = 0;
for (reg_t i = 0; i < N_HPMCOUNTERS; ++i) {
bool of = state->mevent[i]->read() & MHPMEVENT_OF;
val |= of << (i + FIRST_HPMCOUNTER);
}
/* In M and S modes, scountovf bit X is readable when mcounteren bit X is set, */
/* and otherwise reads as zero. Similarly, in VS mode, scountovf bit X is readable */
/* when mcounteren bit X and hcounteren bit X are both set, and otherwise reads as zero. */
val &= state->mcounteren->read();
if (state->v)
val &= state->hcounteren->read();
return val;
}
bool scountovf_csr_t::unlogged_write(const reg_t UNUSED val) noexcept {
/* this function is unused */
return false;
}
// implement class jvt_csr_t
jvt_csr_t::jvt_csr_t(processor_t* const proc, const reg_t addr, const reg_t init):
basic_csr_t(proc, addr, init) {
}
void jvt_csr_t::verify_permissions(insn_t insn, bool write) const {
basic_csr_t::verify_permissions(insn, write);
if (!proc->extension_enabled(EXT_ZCMT))
throw trap_illegal_instruction(insn.bits());
if (proc->extension_enabled(EXT_SMSTATEEN)) {
if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & SSTATEEN0_JVT))
throw trap_illegal_instruction(insn.bits());
if (state->v && !(state->hstateen[0]->read() & SSTATEEN0_JVT))
throw trap_virtual_instruction(insn.bits());
if ((proc->extension_enabled('S') && state->prv < PRV_S) && !(state->sstateen[0]->read() & SSTATEEN0_JVT)) {
if (state->v)
throw trap_virtual_instruction(insn.bits());
else
throw trap_illegal_instruction(insn.bits());
}
}
}
virtualized_indirect_csr_t::virtualized_indirect_csr_t(processor_t* const proc, csr_t_p orig, csr_t_p virt):
virtualized_csr_t(proc, orig, virt) {
}
void virtualized_indirect_csr_t::verify_permissions(insn_t insn, bool write) const {
virtualized_csr_t::verify_permissions(insn, write);
if (state->v)
virt_csr->verify_permissions(insn, write);
else
orig_csr->verify_permissions(insn, write);
}
sscsrind_reg_csr_t::sscsrind_reg_csr_t(processor_t* const proc, const reg_t addr, csr_t_p iselect) :
csr_t(proc, addr),
iselect(iselect) {
}
void sscsrind_reg_csr_t::verify_permissions(insn_t insn, bool write) const {
// Don't call base verify_permission for VS registers remapped to S-mode
if (insn.csr() == address)
csr_t::verify_permissions(insn, write);
csr_t_p proxy_csr = get_reg();
if (proxy_csr == nullptr) {
if (!state->v) {
throw trap_illegal_instruction(insn.bits());
} else {
throw trap_virtual_instruction(insn.bits());
}
}
proxy_csr->verify_permissions(insn, write);
}
reg_t sscsrind_reg_csr_t::read() const noexcept {
csr_t_p target_csr = get_reg();
if (target_csr != nullptr) {
return target_csr->read();
}
return 0;
}
bool sscsrind_reg_csr_t::unlogged_write(const reg_t val) noexcept {
csr_t_p proxy_csr = get_reg();
if (proxy_csr != nullptr) {
proxy_csr->write(val);
}
return false;
}
// Returns the actual CSR that maps to value in *siselect or nullptr if no mapping exists
csr_t_p sscsrind_reg_csr_t::get_reg() const noexcept {
auto proxy = ireg_proxy;
auto isel = iselect->read();
auto it = proxy.find(isel);
return it != proxy.end() ? it->second : nullptr;
}
void sscsrind_reg_csr_t::add_ireg_proxy(const reg_t iselect_value, csr_t_p csr) {
ireg_proxy[iselect_value] = csr;
}
smcntrpmf_csr_t::smcntrpmf_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init) : masked_csr_t(proc, addr, mask, init) {
}
reg_t smcntrpmf_csr_t::read_prev() const noexcept {
reg_t val = prev_val.value_or(read());
return val;
}
void smcntrpmf_csr_t::reset_prev() noexcept {
prev_val.reset();
}
bool smcntrpmf_csr_t::unlogged_write(const reg_t val) noexcept {
prev_val = read();
return masked_csr_t::unlogged_write(val);
}
srmcfg_csr_t::srmcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init):
masked_csr_t(proc, addr, mask, init) {
}
void srmcfg_csr_t::verify_permissions(insn_t insn, bool write) const {
if (!proc->extension_enabled(EXT_SSQOSID))
throw trap_illegal_instruction(insn.bits());
if (proc->extension_enabled(EXT_SMSTATEEN)) {
if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & MSTATEEN0_PRIV114))
throw trap_illegal_instruction(insn.bits());
}
if (state->v)
throw trap_virtual_instruction(insn.bits());
if (state->prv < PRV_S) {
throw trap_illegal_instruction(insn.bits());
}
}
hvip_csr_t::hvip_csr_t(processor_t* const proc, const reg_t addr, const reg_t init):
basic_csr_t(proc, addr, init) {
}
reg_t hvip_csr_t::read() const noexcept {
return basic_csr_t::read() | (state->mip->read() & MIP_VSSIP); // hvip.VSSIP is an alias of mip.VSSIP
}
bool hvip_csr_t::unlogged_write(const reg_t val) noexcept {
state->mip->write_with_mask(MIP_VSSIP, val); // hvip.VSSIP is an alias of mip.VSSIP
return basic_csr_t::unlogged_write(val & (MIP_VSEIP | MIP_VSTIP));
}
ssp_csr_t::ssp_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init):
masked_csr_t(proc, addr, mask, init) {
}
void ssp_csr_t::verify_permissions(insn_t insn, bool write) const {
masked_csr_t::verify_permissions(insn, write);
DECLARE_XENVCFG_VARS(SSE);
require_envcfg(SSE);
}
mtval2_csr_t::mtval2_csr_t(processor_t* const proc, const reg_t addr):
hypervisor_csr_t(proc, addr) {
}
void mtval2_csr_t::verify_permissions(insn_t insn, bool write) const {
basic_csr_t::verify_permissions(insn, write);
if (!proc->extension_enabled('H') && !proc->extension_enabled(EXT_SSDBLTRP))
throw trap_illegal_instruction(insn.bits());
}
hstatus_csr_t::hstatus_csr_t(processor_t* const proc, const reg_t addr):
basic_csr_t(proc, addr, set_field((reg_t)0, HSTATUS_VSXL, xlen_to_uxl(proc->get_const_xlen()))) {
}
bool hstatus_csr_t::unlogged_write(const reg_t val) noexcept {
const reg_t mask = HSTATUS_VTSR | HSTATUS_VTW
| (proc->supports_impl(IMPL_MMU) ? HSTATUS_VTVM : 0)
| (proc->extension_enabled(EXT_SSNPM) ? HSTATUS_HUPMM : 0)
| HSTATUS_HU | HSTATUS_SPVP | HSTATUS_SPV | HSTATUS_GVA;
const reg_t pmm_reserved = 1; // Reserved value of mseccfg.PMM
reg_t pmm = get_field(val, HSTATUS_HUPMM);
const reg_t adjusted_val = set_field(val, HSTATUS_HUPMM, pmm != pmm_reserved ? pmm : 0);
const reg_t new_hstatus = (read() & ~mask) | (adjusted_val & mask);
if (get_field(new_hstatus, HSTATUS_HUPMM) != get_field(read(), HSTATUS_HUPMM))
proc->get_mmu()->flush_tlb();
return basic_csr_t::unlogged_write(new_hstatus);
}
|