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| author | Ved Shanbhogue <ved@rivosinc.com> | 2024-01-10 15:23:46 -0600 |
|---|---|---|
| committer | Ved Shanbhogue <ved@rivosinc.com> | 2024-01-10 15:26:09 -0600 |
| commit | 075af7fd61f97e307ab550c0e3688d2230797605 (patch) | |
| tree | 028c19d6f45ef7ccb1fdaf1f74f347e99d71554d /riscv/csrs.cc | |
| parent | 5fa1cd541872ac601580fda58eb093aaf12aab32 (diff) | |
| download | riscv-isa-sim-075af7fd61f97e307ab550c0e3688d2230797605.zip riscv-isa-sim-075af7fd61f97e307ab550c0e3688d2230797605.tar.gz riscv-isa-sim-075af7fd61f97e307ab550c0e3688d2230797605.tar.bz2 | |
B=Zba+Zbb+Zbs
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index ce14b28..b809f18 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -622,9 +622,10 @@ bool sstatus_csr_t::enabled(const reg_t which) { misa_csr_t::misa_csr_t(processor_t* const proc, const reg_t addr, const reg_t max_isa): basic_csr_t(proc, addr, max_isa), max_isa(max_isa), - write_mask(max_isa & (0 // allow MAFDQCHV bits in MISA to be modified + write_mask(max_isa & (0 // allow MABFDQCHV bits in MISA to be modified | (1L << ('M' - 'A')) | (1L << ('A' - 'A')) + | (1L << ('B' - 'A')) | (1L << ('F' - 'A')) | (1L << ('D' - 'A')) | (1L << ('Q' - 'A')) @@ -666,6 +667,10 @@ bool misa_csr_t::unlogged_write(const reg_t val) noexcept { proc->set_extension_enable(EXT_ZVFH, (new_misa & (1L << ('V' - 'A'))) && proc->extension_enabled(EXT_ZFHMIN)); proc->set_extension_enable(EXT_ZVFHMIN, new_misa & (1L << ('V' - 'A'))); + proc->set_extension_enable(EXT_ZBA, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B')); + proc->set_extension_enable(EXT_ZBB, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B')); + proc->set_extension_enable(EXT_ZBS, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B')); + // update the hypervisor-only bits in MEDELEG and other CSRs if (!new_h && prev_h) { reg_t hypervisor_exceptions = 0 |