| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 3 days | Merge pull request #1705 from rpsene/masterHEADmaster | Jerry Zhao | 1 | -0/+1 | |
| 3 days | Fix: Add missing <stdexcept> header for std::logic_error | Rafael Sene | 1 | -0/+1 | |
| - Included <stdexcept> in isa_parser.cc to resolve compilation error due to missing type 'std::logic_error'. Signed-off-by: Rafael Sene <rafael@riscv.org> | |||||
| 3 days | Merge pull request #1701 from riscv-software-src/zvl_zve | Jerry Zhao | 15 | -119/+93 | |
| Correctly determine vector capability from v/zve/zvl ISA strings, remove --varch | |||||
| 3 days | Merge pull request #1704 from riscv-software-src/thread-local-again | Andrew Waterman | 1 | -2/+1 | |
| Fix C/C++ thread-local linkage differently | |||||
| 3 days | Fix C/C++ thread-local linkage differently | Andrew Waterman | 1 | -2/+1 | |
| Just admit Mac OS is broken, so explicitly special-case it. See #1689 and #1703 | |||||
| 4 days | Vector-fp instructions depend on zve, not F/D | Jerry Zhao | 2 | -10/+12 | |
| 4 days | Restrict spike to vlen <= 4096 | Jerry Zhao | 1 | -0/+4 | |
| 4 days | Remove all --varch parsing | Jerry Zhao | 9 | -93/+1 | |
| 4 days | Switch to Zvl/Zve parsing from isa_parser, instead of varch | Jerry Zhao | 1 | -1/+4 | |
| 4 days | Disallow any vector, not just V, when no __int128 type is present | Jerry Zhao | 1 | -1/+1 | |
| 4 days | Relax require_vector check for misa.V | Jerry Zhao | 1 | -2/+0 | |
| 4 days | Relax mstatus.vs dependency on full V | Jerry Zhao | 2 | -1/+5 | |
| 4 days | Relax vector_csr dependency on 'V' | Jerry Zhao | 1 | -4/+0 | |
| 4 days | Relax zvfh/zvfhmin dependency on V, they only actually depend on Zve | Jerry Zhao | 1 | -3/+0 | |
| 4 days | Allow disassembly from implementations that are not full V | Jerry Zhao | 1 | -1/+1 | |
| 4 days | Relax has_fs dependency on misa.v | Jerry Zhao | 1 | -2/+1 | |
| isa_parser should already require any Zvef or Zved extensions imply F/D | |||||
| 4 days | Add accessors to isa_parser's VLEN/ELEN | Jerry Zhao | 1 | -0/+3 | |
| 4 days | Add Zvl/Zve validation to isa_parser | Jerry Zhao | 1 | -0/+21 | |
| 4 days | Add isa_parser parsing for zvl/zve | Jerry Zhao | 2 | -1/+40 | |
| 4 days | Merge pull request #1702 from riscv-software-src/fix-1696 | Andrew Waterman | 1 | -20/+20 | |
| In isa_parser, move extensionology code before error-checking code | |||||
| 4 days | In isa_parser, move extensionology code before error-checking code | Andrew Waterman | 1 | -20/+20 | |
| Resolves #1696 | |||||
| 4 days | Merge pull request #1695 from riscv-software-src/bf16-ops | Andrew Waterman | 10 | -4/+443 | |
| Add several BF16 ops to SoftFloat | |||||
| 4 days | Merge pull request #1690 from riscv-software-src/fix-warnings | Jerry Zhao | 2 | -17/+17 | |
| Fix a few compile warnings | |||||
| 6 days | Add several BF16 ops to SoftFloat | Andrew Waterman | 10 | -0/+435 | |
| 7 days | Merge pull request #1694 from Du-Chao/master | Andrew Waterman | 1 | -1/+1 | |
| Add a prerequisite for building | |||||
| 7 days | Add a prerequisite for building | Chao Du | 1 | -1/+1 | |
| Otherwise, configure will fail with 'Could not find a version of the Boost::Asio library!' | |||||
| 7 days | Consistently order BF16 routines in Makefile and softfloat.h | Andrew Waterman | 2 | -4/+8 | |
| 11 days | Merge pull request #1689 from riscv-software-src/rounding-mode-thread-local | Andrew Waterman | 1 | -2/+5 | |
| Make softfloat's rounding mode thread-local | |||||
| 11 days | Make softfloat's rounding mode thread-local | Andrew Waterman | 1 | -2/+5 | |
| This has no effect on Spike itself, but it might matter for anyone who's using Spike as a library in a multithreaded program. | |||||
| 11 days | Merge branch 'NXP-zilsd' | Andrew Waterman | 11 | -17/+83 | |
| 11 days | Adding Zilsd and Zcmlsd extensions (Load/store pair for RV32) | Christian Herber | 11 | -17/+83 | |
| 12 days | Fix a few compile warnings | Andrew Waterman | 2 | -17/+17 | |
| 13 days | Merge pull request #1679 from akifejaz/vector-crypto | Andrew Waterman | 1 | -0/+10 | |
| Updated README with supported Vector Cryptography Extensions | |||||
| 13 days | Merge branch 'master' into vector-crypto | Akif Ejaz | 20 | -139/+199 | |
| 13 days | Merge pull request #1687 from riscv-software-src/flw-overlap | Andrew Waterman | 13 | -124/+179 | |
| Separate RV32 and RV64 C instructions into separate files | |||||
| 13 days | Validate contents of overlap list in CI | Andrew Waterman | 1 | -13/+32 | |
| 13 days | Separate RV32 and RV64 C instructions into separate files | Andrew Waterman | 10 | -33/+31 | |
| 13 days | Improve hit rate of opcode cache to compensate for not mutating insn list | Andrew Waterman | 2 | -17/+58 | |
| 13 days | Compensate for perf loss of not mutating insn list by presorting it | Andrew Waterman | 1 | -7/+7 | |
| 13 days | Keep potentially overlapping instructions in order at head of list | Andrew Waterman | 1 | -20/+32 | |
| 13 days | Preserve the ordering of the instruction list | Andrew Waterman | 1 | -22/+2 | |
| 13 days | Add comments to overlap list | Andrew Waterman | 1 | -0/+9 | |
| 13 days | Refine Zicfiss overlap list | Andrew Waterman | 1 | -2/+5 | |
| We get better error checking if we list only the more specific instructions and omit the more general ones (mop.r.N/mop.rr.N). | |||||
| 13 days | Remove unnecessary instructions from overlap list | Andrew Waterman | 1 | -11/+0 | |
| - c.fsdsp need not be listed since cm.push etc. are listed - mop.r.28/mop.rr.7 don't have corresponding files in riscv/insns/ - the rest are just erroneous | |||||
| 13 days | Add missing instructions to Makefile | Andrew Waterman | 1 | -0/+4 | |
| 13 days | Merge pull request #1688 from YenHaoChen/pr-tcontrol | Andrew Waterman | 5 | -1/+9 | |
| triggers: implement tcontrol | |||||
| 2024-06-11 | triggers: implement tcontrol | YenHaoChen | 5 | -1/+9 | |
| Implement Debug spec Section 5.7.6. Trigger Control (tcontrol). This commit lets tcontrol be read-only 0 if number of triggers is 0. | |||||
| 2024-05-31 | Merge pull request #1684 from riscv-software-src/simplify-zicfilp | Andrew Waterman | 6 | -14/+11 | |
| Avoid checking ELP before every instruction fetch | |||||
| 2024-05-31 | Avoid checking ELP before every instruction fetch | Andrew Waterman | 6 | -13/+12 | |
| Serialize after setting ELP. That way, we can hoist the check outside of the main simulation loop. | |||||
| 2024-05-31 | No need to check if Zicfilp is enabled before checking ELP | Andrew Waterman | 1 | -3/+1 | |
| ELP will be zero if Zicfilp is not enabled. | |||||
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index : rocket-tools/riscv-isa-sim.git | |
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