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| author | YenHaoChen <howard25336284@gmail.com> | 2024-04-09 09:13:24 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2024-04-09 09:29:00 +0800 |
| commit | a101bfebe07c92447b8239737c1a18702e63df98 (patch) | |
| tree | 8a57198d32c410f260650a17ffb9c87cb62e5209 /riscv/csrs.cc | |
| parent | 3427b459f88d2334368a1abbdf5a3000957f08e8 (diff) | |
| download | riscv-isa-sim-a101bfebe07c92447b8239737c1a18702e63df98.zip riscv-isa-sim-a101bfebe07c92447b8239737c1a18702e63df98.tar.gz riscv-isa-sim-a101bfebe07c92447b8239737c1a18702e63df98.tar.bz2 | |
Ignore writes to henvcfg fields (PBMTE, STCE, and ADUE) when read-only 0
The henvcfg fields, i.e., PBMTE, STCE, and ADUE, are read-only 0 when
the corresponding bits in menvcfg are 0. Besides the reading behavior,
the spec also specified the writing behavior, i.e., ignoring writes.
This commit ignores writes to the henvcfg fields when read-only 0.
Reference: https://github.com/riscv/riscv-isa-manual/issues/1312
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 4900581..4a612e5 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1549,6 +1549,11 @@ void henvcfg_csr_t::verify_permissions(insn_t insn, bool write) const { masked_csr_t::verify_permissions(insn, write); } +bool henvcfg_csr_t::unlogged_write(const reg_t val) noexcept { + const reg_t mask = menvcfg->read() | ~(MENVCFG_PBMTE | MENVCFG_STCE | MENVCFG_ADUE); + return envcfg_csr_t::unlogged_write((masked_csr_t::read() & ~mask) | (val & mask)); +} + stimecmp_csr_t::stimecmp_csr_t(processor_t* const proc, const reg_t addr, const reg_t imask): basic_csr_t(proc, addr, 0), intr_mask(imask) { } |