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| author | Ved Shanbhogue <91900059+ved-rivos@users.noreply.github.com> | 2024-01-10 16:08:54 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-10 16:08:54 -0600 |
| commit | 4a59b90c0f29fb223775388a1cf4d505e724b833 (patch) | |
| tree | b35557ec4d3a598408e1fa95e21f1dfe209f435e /riscv/csrs.cc | |
| parent | 0bf0a60ad870ba3d59f87c03b41b6d06ca5fa30c (diff) | |
| parent | de24759869abcd93f16be1fd10d56e1c547f57bc (diff) | |
| download | riscv-isa-sim-4a59b90c0f29fb223775388a1cf4d505e724b833.zip riscv-isa-sim-4a59b90c0f29fb223775388a1cf4d505e724b833.tar.gz riscv-isa-sim-4a59b90c0f29fb223775388a1cf4d505e724b833.tar.bz2 | |
Merge branch 'master' into zaamo_zalrsc
Signed-off-by: Ved Shanbhogue <91900059+ved-rivos@users.noreply.github.com>
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index b76b496..38c9a10 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -672,6 +672,10 @@ bool misa_csr_t::unlogged_write(const reg_t val) noexcept { proc->set_extension_enable(EXT_ZBB, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B')); proc->set_extension_enable(EXT_ZBS, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B')); + proc->set_extension_enable(EXT_ZBA, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B')); + proc->set_extension_enable(EXT_ZBB, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B')); + proc->set_extension_enable(EXT_ZBS, (new_misa & (1L << ('B' - 'A'))) || !proc->get_isa().extension_enabled('B')); + // update the hypervisor-only bits in MEDELEG and other CSRs if (!new_h && prev_h) { reg_t hypervisor_exceptions = 0 |