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| author | Andrew Waterman <andrew@sifive.com> | 2024-05-01 16:25:46 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-05-01 16:53:06 -0700 |
| commit | c9468f6e024abb6d620ace295ef6e2e58e8f7eb2 (patch) | |
| tree | 9be4f9d3cbe9ff9321d64109be58b3a0ba605654 /riscv/csrs.cc | |
| parent | c4edeabbe756b2527a63970492dfb2239953a990 (diff) | |
| download | riscv-isa-sim-c9468f6e024abb6d620ace295ef6e2e58e8f7eb2.zip riscv-isa-sim-c9468f6e024abb6d620ace295ef6e2e58e8f7eb2.tar.gz riscv-isa-sim-c9468f6e024abb6d620ace295ef6e2e58e8f7eb2.tar.bz2 | |
Remove Zbpbo, Zpn, and Zpsfoperand implementation
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index b4c6b6a..95638d3 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1452,8 +1452,6 @@ vxsat_csr_t::vxsat_csr_t(processor_t* const proc, const reg_t addr): void vxsat_csr_t::verify_permissions(insn_t insn, bool write) const { require_vector_vs; - if (!proc->extension_enabled('V') && !proc->extension_enabled(EXT_ZPN)) - throw trap_illegal_instruction(insn.bits()); masked_csr_t::verify_permissions(insn, write); } |