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| author | Ming-Yi Lai <ming-yi.lai@mediatek.com> | 2024-01-05 11:37:35 +0800 |
|---|---|---|
| committer | Ming-Yi Lai <ming-yi.lai@mediatek.com> | 2024-03-06 17:21:00 +0800 |
| commit | 7b5eba94285f1d12e8268899d3276bd0ff21d9c4 (patch) | |
| tree | e02d84201d925528d628df22f758e03aa103dfed /riscv/csrs.cc | |
| parent | 5ca914b13c78cb25e61a8bad8f2cf84024c4eb44 (diff) | |
| download | riscv-isa-sim-7b5eba94285f1d12e8268899d3276bd0ff21d9c4.zip riscv-isa-sim-7b5eba94285f1d12e8268899d3276bd0ff21d9c4.tar.gz riscv-isa-sim-7b5eba94285f1d12e8268899d3276bd0ff21d9c4.tar.bz2 | |
Zicfilp: Preserve expected landing pad state on traps
Diffstat (limited to 'riscv/csrs.cc')
| -rw-r--r-- | riscv/csrs.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 50fb1a2..728d671 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1337,10 +1337,12 @@ bool dcsr_csr_t::unlogged_write(const reg_t val) noexcept { return true; } -void dcsr_csr_t::write_cause_and_prv(uint8_t cause, reg_t prv, bool v) noexcept { +void dcsr_csr_t::update_fields(const uint8_t cause, const reg_t prv, + const bool v, const elp_t pelp) noexcept { this->cause = cause; this->prv = prv; this->v = v; + this->pelp = pelp; log_write(); } |