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AgeCommit message (Expand)AuthorFilesLines
2024-05-30Support more basic testing of Zca instructionsAndrew Waterman1-13/+13
2024-05-30Support basic testing of more Zca instructionsAndrew Waterman1-76/+76
2024-03-19ma_addr: permit access faults in lieu of misaligned exceptionsAndrew Waterman1-1/+6
2024-02-18Fix breakpoint testAndrew Waterman1-0/+3
2024-02-19Add zbs test casesRoger Chang19-2/+773
2024-02-19Add zbc test casesRoger Chang9-2/+520
2024-02-19Add zbb test casesRoger Chang45-2/+2665
2024-02-19Add zba test casesRoger Chang14-2/+958
2024-02-03If Svnapot is not implemented, skip the test.Eiji Yoshiya1-0/+11
2024-01-29Uses appropriate addi instruction in lrsc test.Lucas Clemente Vella1-1/+1
2023-04-06Augment LR/SC test to test that SC-after-failed-SC failsAndrew Waterman1-2/+5
2023-04-06Merge pull request #466 from riscv-software-src/spike-zicntrAndrew Waterman1-2/+2
2023-04-06Merge pull request #464 from nervosnetwork/amocmp_wAndrew Waterman4-1/+40
2023-04-06Include Zicntr in Spike ISA stringAndrew Waterman1-2/+2
2023-04-06Add more tests for amomax/maxu/min/minu_wmohanson4-1/+40
2023-03-16Fix breakpoint.S failing when tcontrol is implemented (#463)Luke Wren1-0/+10
2023-02-27rv32ui test misaligned load/store data (#459)Jesse Taube3-5/+9
2023-02-13Fix ma_fetch test for norvc (#454)Yujia Qiao1-1/+1
2023-01-19Fix ma_fetch test for writable misa.C (#449)Jerry Zhao1-3/+3
2023-01-19Pass --misaligned flag to Spike to run ISA tests (#445)Andrew Waterman1-2/+2
2022-12-28Fix ma_fetch test to support systems where no RVC does not imply IALIGN=32Jerry Zhao1-9/+31
2022-12-07zicntr: separate cycle/instret accessibility test (#439)Chih-Min Chao5-16/+69
2022-09-27rv64ui test misaligned load/store data (#410)John Ingalls2-0/+388
2022-09-27zicboz: comment # (#412)John Ingalls1-1/+1
2022-09-26zicbo test zero (#411)John Ingalls3-2/+49
2022-06-09Test misaligned stores. (#397)Tim Newsome8-0/+158
2022-06-07Test misaligned loads.Tim Newsome8-0/+160
2022-06-07Set TESTNUM before executing code.Tim Newsome3-6/+4
2022-06-06Revert unaligned tests.Tim Newsome3-51/+1
2022-06-06Test unaligned ld accesses.Tim Newsome1-0/+27
2022-06-06Add unaligned test cases for lwTim Newsome1-0/+23
2022-06-06Set TESTNUM before executing code.Tim Newsome1-1/+1
2022-05-28Permit mtval to be zero in misaligned address test, fixes #389 (#390)Luke Wren1-0/+2
2022-03-08Add Zfh and Svnapot to Spike ISA stringAndrew Waterman1-2/+2
2021-07-22Fix #352 (#353)Daniel Lustig1-2/+2
2021-07-21Move the Svnapot test to its own folder (#351)Daniel Lustig4-1/+10
2021-07-19Add a test for Svnapot (#349)Daniel Lustig2-0/+173
2021-06-01Enable access to cycle counter before trying to write itAndrew Waterman1-0/+13
2021-06-01Test all four ways of reading a read-only CSRAndrew Waterman1-0/+8
2021-05-12Fix for rv64mi/sbreak and rv64mi/scall that I broke in my previous commit: (#...SLAMET RIANTO2-0/+2
2021-05-10Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support C...SLAMET RIANTO3-0/+52
2021-02-01Align mtvec in rv32mi-p-shamt testAndrew Waterman1-0/+1
2021-01-08Don't rely on the implementation-specific WFI time limit (#318)Paul Donahue1-18/+0
2021-01-04Disable rv32ua/rv64ua LR/SC test case 4 (#316)Ben Marshall1-8/+14
2020-12-16Refactor rv64ud structural test to match format of other tests (#311)Kathlene Hurt1-11/+13
2020-12-08Add rd=x0 test case to csr test (#308)Takahiro1-0/+1
2020-12-07Fix minor typo (#307)Takahiro1-1/+1
2020-11-20Only attempt to build tests supported by compilerAndrew Waterman19-38/+6
2020-11-11add zfh (float16) test case and related macros (#301)Chih-Min Chao26-0/+769
2020-10-19use registers present on rv32e (#299)Sandeep Rajendran1-4/+4
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