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| author | Luke Wren <wren6991@gmail.com> | 2023-03-16 21:56:55 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-03-16 14:56:55 -0700 |
| commit | 08698050b84886b0b52458f46bd801267eb9c0ce (patch) | |
| tree | 414845db4f50394645d3da7e95a18919b575d2e2 /isa | |
| parent | 654419c440f2c7b452129b0d63a21528d12e9a04 (diff) | |
| download | riscv-tests-08698050b84886b0b52458f46bd801267eb9c0ce.zip riscv-tests-08698050b84886b0b52458f46bd801267eb9c0ce.tar.gz riscv-tests-08698050b84886b0b52458f46bd801267eb9c0ce.tar.bz2 | |
Fix breakpoint.S failing when tcontrol is implemented (#463)
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64mi/breakpoint.S | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index 252a696..1223f71 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -16,6 +16,16 @@ RVTEST_CODE_BEGIN # Set up breakpoint to trap on M-mode fetches. li TESTNUM, 2 + # Set tcontrol.mte, otherwise breakpoints are disabled. This may trap, + # because tcontrol is an optional register. + la a0, 1f + csrrw a0, mtvec, a0 + li a1, 0x8 + csrs tcontrol, a1 +.p2align 2 +1: + csrw mtvec, a0 + # Skip tselect if hard-wired. csrw tselect, x0 csrr a1, tselect |