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| author | mohanson <mohanson@outlook.com> | 2023-04-06 15:24:28 +0800 |
|---|---|---|
| committer | mohanson <mohanson@outlook.com> | 2023-04-06 15:27:04 +0800 |
| commit | 40a91b6839ef9d9188cf48e7535053e75f5cf44b (patch) | |
| tree | 0505a5dacd52272bdeccce83485259bc1bce1cd8 /isa | |
| parent | e30978a71921159aec38eeefd848fca4ed39a826 (diff) | |
| download | riscv-tests-40a91b6839ef9d9188cf48e7535053e75f5cf44b.zip riscv-tests-40a91b6839ef9d9188cf48e7535053e75f5cf44b.tar.gz riscv-tests-40a91b6839ef9d9188cf48e7535053e75f5cf44b.tar.bz2 | |
Add more tests for amomax/maxu/min/minu_w
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64ua/amomax_w.S | 10 | ||||
| -rw-r--r-- | isa/rv64ua/amomaxu_w.S | 10 | ||||
| -rw-r--r-- | isa/rv64ua/amomin_w.S | 10 | ||||
| -rw-r--r-- | isa/rv64ua/amominu_w.S | 11 |
4 files changed, 40 insertions, 1 deletions
diff --git a/isa/rv64ua/amomax_w.S b/isa/rv64ua/amomax_w.S index f986205..2c42982 100644 --- a/isa/rv64ua/amomax_w.S +++ b/isa/rv64ua/amomax_w.S @@ -31,6 +31,16 @@ RVTEST_CODE_BEGIN TEST_CASE(5, a5, 1, lw a5, 0(a3)) + TEST_CASE(6, a4, 1, \ + li a0, 0x0000000000000001; \ + li a1, 0x0000000080000000; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(7, a5, 1, lw a5, 0(a3)) + TEST_PASSFAIL RVTEST_CODE_END diff --git a/isa/rv64ua/amomaxu_w.S b/isa/rv64ua/amomaxu_w.S index eb27d07..6eabcd2 100644 --- a/isa/rv64ua/amomaxu_w.S +++ b/isa/rv64ua/amomaxu_w.S @@ -31,6 +31,16 @@ RVTEST_CODE_BEGIN TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + TEST_CASE(6, a4, 1, \ + li a0, 0x0000000000000001; \ + li a1, 0x8000000000000000; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(7, a5, 1, lw a5, 0(a3)) + TEST_PASSFAIL RVTEST_CODE_END diff --git a/isa/rv64ua/amomin_w.S b/isa/rv64ua/amomin_w.S index 1337d2c..754f64d 100644 --- a/isa/rv64ua/amomin_w.S +++ b/isa/rv64ua/amomin_w.S @@ -31,6 +31,16 @@ RVTEST_CODE_BEGIN TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + TEST_CASE(6, a4, 1, \ + li a0, 0x0000000000000001; \ + li a1, 0x0000000080000000; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(7, a5, 0xffffffff80000000, lw a5, 0(a3)) + TEST_PASSFAIL RVTEST_CODE_END diff --git a/isa/rv64ua/amominu_w.S b/isa/rv64ua/amominu_w.S index f45f856..d04a650 100644 --- a/isa/rv64ua/amominu_w.S +++ b/isa/rv64ua/amominu_w.S @@ -31,6 +31,16 @@ RVTEST_CODE_BEGIN TEST_CASE(5, a5, 0, lw a5, 0(a3)) + TEST_CASE(6, a4, 1, \ + li a0, 0x0000000000000001; \ + li a1, 0x8000000000000000; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(7, a5, 0, lw a5, 0(a3)) + TEST_PASSFAIL RVTEST_CODE_END @@ -46,4 +56,3 @@ RVTEST_DATA_END .align 3 amo_operand: .dword 0 - |