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| author | Luke Wren <wren6991@gmail.com> | 2022-05-29 05:15:52 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-28 21:15:52 -0700 |
| commit | 3dc79832d072ccbb6ebd1b7115c887fb621be5d3 (patch) | |
| tree | 3a007a490e578ea55b27bd56d606af3c814559e5 /isa | |
| parent | fd6e7ed1707b3449f9673fa6b3bc1e422af4669b (diff) | |
| download | riscv-tests-3dc79832d072ccbb6ebd1b7115c887fb621be5d3.zip riscv-tests-3dc79832d072ccbb6ebd1b7115c887fb621be5d3.tar.gz riscv-tests-3dc79832d072ccbb6ebd1b7115c887fb621be5d3.tar.bz2 | |
Permit mtval to be zero in misaligned address test, fixes #389 (#390)
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64mi/ma_addr.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S index 721ac6a..f02a1af 100644 --- a/isa/rv64mi/ma_addr.S +++ b/isa/rv64mi/ma_addr.S @@ -99,10 +99,12 @@ mtvec_handler: bne t0, s1, fail csrr t0, mbadaddr + beqz t0, 1f bne t0, t1, fail lb t0, (t0) beqz t0, fail +1: csrw mepc, t2 mret |