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| author | Takahiro <hogehoge@gachapin.jp> | 2020-12-07 16:15:49 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-07 16:15:49 -0800 |
| commit | 4a54e2b7d89343798fcbbdf07d9a061d8a5b651e (patch) | |
| tree | 4ed131efff19ab0c8080ae1ebba1a9144c6fd155 /isa | |
| parent | 58eb560a84ea2d6a392f7e75bba649a0c5946617 (diff) | |
| download | riscv-tests-4a54e2b7d89343798fcbbdf07d9a061d8a5b651e.zip riscv-tests-4a54e2b7d89343798fcbbdf07d9a061d8a5b651e.tar.gz riscv-tests-4a54e2b7d89343798fcbbdf07d9a061d8a5b651e.tar.bz2 | |
Fix minor typo (#307)
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64mi/mcsr.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S index e0256e7..03cf29a 100644 --- a/isa/rv64mi/mcsr.S +++ b/isa/rv64mi/mcsr.S @@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN csrr a0, marchid csrr a0, mvendorid - # Check that writing hte following CSRs doesn't cause an exception + # Check that writing the following CSRs doesn't cause an exception li t0, 0 csrs mtvec, t0 csrs mepc, t0 |