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| author | Andrew Waterman <andrew@sifive.com> | 2022-03-08 01:07:00 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-03-08 01:07:00 -0800 |
| commit | 3e2bf06b071a77ae62c09bf07c5229d1f9397d94 (patch) | |
| tree | e08b31dabac2e47b0f509f692b9335ca5ebac66b /isa | |
| parent | bd050de178cb1ffcfaae6bf1c79e6e640600b22f (diff) | |
| download | riscv-tests-3e2bf06b071a77ae62c09bf07c5229d1f9397d94.zip riscv-tests-3e2bf06b071a77ae62c09bf07c5229d1f9397d94.tar.gz riscv-tests-3e2bf06b071a77ae62c09bf07c5229d1f9397d94.tar.bz2 | |
Add Zfh and Svnapot to Spike ISA string
Otherwise, "make run" doesn't work.
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/isa/Makefile b/isa/Makefile index a514cb2..681f322 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -49,10 +49,10 @@ vpath %.S $(src_dir) $(RISCV_OBJDUMP) $< > $@ %.out: % - $(RISCV_SIM) --isa=rv64gc $< 2> $@ + $(RISCV_SIM) --isa=rv64gc_zfh_svnapot $< 2> $@ %.out32: % - $(RISCV_SIM) --isa=rv32gc $< 2> $@ + $(RISCV_SIM) --isa=rv32gc_zfh_svnapot $< 2> $@ define compile_template |