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| author | Andrew Waterman <andrew@sifive.com> | 2023-01-19 21:55:50 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-01-19 21:55:50 -0800 |
| commit | b771a5e9bb6c70d25473d199e997f19036d7f5b1 (patch) | |
| tree | 58721eb68717fee4f58aa6366bc66e6018b78454 /isa | |
| parent | c84daca8824635b7d896003c78f9c6245997cf7a (diff) | |
| download | riscv-tests-b771a5e9bb6c70d25473d199e997f19036d7f5b1.zip riscv-tests-b771a5e9bb6c70d25473d199e997f19036d7f5b1.tar.gz riscv-tests-b771a5e9bb6c70d25473d199e997f19036d7f5b1.tar.bz2 | |
Pass --misaligned flag to Spike to run ISA tests (#445)
...because the ma_data test requires this feature.
Don't merge until https://github.com/riscv-software-src/riscv-isa-sim/pull/1206 is merged.
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/isa/Makefile b/isa/Makefile index 0203a82..c542f33 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -50,10 +50,10 @@ vpath %.S $(src_dir) $(RISCV_OBJDUMP) $< > $@ %.out: % - $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot $< 2> $@ + $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot --misaligned $< 2> $@ %.out32: % - $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot $< 2> $@ + $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot --misaligned $< 2> $@ define compile_template |