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| author | Andrew Waterman <andrew@sifive.com> | 2023-04-06 10:02:57 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-04-06 10:02:57 -0700 |
| commit | 510ca1e645d3cc2aa3c38398a8bb0f2f67f79f5c (patch) | |
| tree | 10eded469213eb517e01b0f694631edae0d05cbc /isa | |
| parent | c825b1f1678be926b226c74a9ed997a4ea99db98 (diff) | |
| parent | 40a91b6839ef9d9188cf48e7535053e75f5cf44b (diff) | |
| download | riscv-tests-510ca1e645d3cc2aa3c38398a8bb0f2f67f79f5c.zip riscv-tests-510ca1e645d3cc2aa3c38398a8bb0f2f67f79f5c.tar.gz riscv-tests-510ca1e645d3cc2aa3c38398a8bb0f2f67f79f5c.tar.bz2 | |
Merge pull request #464 from nervosnetwork/amocmp_w
Add more tests for amo[max/maxu/min/minu]_w
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64ua/amomax_w.S | 10 | ||||
| -rw-r--r-- | isa/rv64ua/amomaxu_w.S | 10 | ||||
| -rw-r--r-- | isa/rv64ua/amomin_w.S | 10 | ||||
| -rw-r--r-- | isa/rv64ua/amominu_w.S | 11 |
4 files changed, 40 insertions, 1 deletions
diff --git a/isa/rv64ua/amomax_w.S b/isa/rv64ua/amomax_w.S index f986205..2c42982 100644 --- a/isa/rv64ua/amomax_w.S +++ b/isa/rv64ua/amomax_w.S @@ -31,6 +31,16 @@ RVTEST_CODE_BEGIN TEST_CASE(5, a5, 1, lw a5, 0(a3)) + TEST_CASE(6, a4, 1, \ + li a0, 0x0000000000000001; \ + li a1, 0x0000000080000000; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(7, a5, 1, lw a5, 0(a3)) + TEST_PASSFAIL RVTEST_CODE_END diff --git a/isa/rv64ua/amomaxu_w.S b/isa/rv64ua/amomaxu_w.S index eb27d07..6eabcd2 100644 --- a/isa/rv64ua/amomaxu_w.S +++ b/isa/rv64ua/amomaxu_w.S @@ -31,6 +31,16 @@ RVTEST_CODE_BEGIN TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + TEST_CASE(6, a4, 1, \ + li a0, 0x0000000000000001; \ + li a1, 0x8000000000000000; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(7, a5, 1, lw a5, 0(a3)) + TEST_PASSFAIL RVTEST_CODE_END diff --git a/isa/rv64ua/amomin_w.S b/isa/rv64ua/amomin_w.S index 1337d2c..754f64d 100644 --- a/isa/rv64ua/amomin_w.S +++ b/isa/rv64ua/amomin_w.S @@ -31,6 +31,16 @@ RVTEST_CODE_BEGIN TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + TEST_CASE(6, a4, 1, \ + li a0, 0x0000000000000001; \ + li a1, 0x0000000080000000; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(7, a5, 0xffffffff80000000, lw a5, 0(a3)) + TEST_PASSFAIL RVTEST_CODE_END diff --git a/isa/rv64ua/amominu_w.S b/isa/rv64ua/amominu_w.S index f45f856..d04a650 100644 --- a/isa/rv64ua/amominu_w.S +++ b/isa/rv64ua/amominu_w.S @@ -31,6 +31,16 @@ RVTEST_CODE_BEGIN TEST_CASE(5, a5, 0, lw a5, 0(a3)) + TEST_CASE(6, a4, 1, \ + li a0, 0x0000000000000001; \ + li a1, 0x8000000000000000; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(7, a5, 0, lw a5, 0(a3)) + TEST_PASSFAIL RVTEST_CODE_END @@ -46,4 +56,3 @@ RVTEST_DATA_END .align 3 amo_operand: .dword 0 - |