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| author | Jerry Zhao <jerryz123@berkeley.edu> | 2023-01-19 22:02:19 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-01-19 22:02:19 -0800 |
| commit | a6ab6ae6008ffc2ea907ea9f6d2b8379583e7d56 (patch) | |
| tree | 29e5b5d6878ec7170e8ca42346c4347d4f3662d6 /isa | |
| parent | b771a5e9bb6c70d25473d199e997f19036d7f5b1 (diff) | |
| download | riscv-tests-a6ab6ae6008ffc2ea907ea9f6d2b8379583e7d56.zip riscv-tests-a6ab6ae6008ffc2ea907ea9f6d2b8379583e7d56.tar.gz riscv-tests-a6ab6ae6008ffc2ea907ea9f6d2b8379583e7d56.tar.bz2 | |
Fix ma_fetch test for writable misa.C (#449)
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64si/ma_fetch.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S index 22eadc9..255ad48 100644 --- a/isa/rv64si/ma_fetch.S +++ b/isa/rv64si/ma_fetch.S @@ -120,10 +120,10 @@ RVTEST_CODE_BEGIN bnez t2, pass # Skip if clearing misa.C does not set IALIGN=32 - csrr t0, mepc + csrr t0, mtvec la t1, 1f addi t1, t1, 2 - csrw mepc, t1 + csrw mtvec, t1 j 1f .option rvc @@ -132,7 +132,7 @@ RVTEST_CODE_BEGIN j pass .option norvc 2: - csrw mepc, t0 + csrw mtvec, t0 csrsi misa, 1 << ('c' - 'a') # IALIGN=32 cannot be set if doing so would cause a misaligned instruction |