diff options
| author | Andrew Waterman <andrew@sifive.com> | 2023-04-06 10:03:14 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-04-06 10:03:14 -0700 |
| commit | aaae4e7d20831ac8383350ff8c859994012f3528 (patch) | |
| tree | 0638a0406503054566ff2dd7794bddc3100c834c /isa | |
| parent | 510ca1e645d3cc2aa3c38398a8bb0f2f67f79f5c (diff) | |
| parent | 385ca8fa6de6289ed26f85cde11cedcdb805c60e (diff) | |
| download | riscv-tests-aaae4e7d20831ac8383350ff8c859994012f3528.zip riscv-tests-aaae4e7d20831ac8383350ff8c859994012f3528.tar.gz riscv-tests-aaae4e7d20831ac8383350ff8c859994012f3528.tar.bz2 | |
Merge pull request #466 from riscv-software-src/spike-zicntr
Include Zicntr in Spike ISA string
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/isa/Makefile b/isa/Makefile index c542f33..d66b901 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -50,10 +50,10 @@ vpath %.S $(src_dir) $(RISCV_OBJDUMP) $< > $@ %.out: % - $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr --misaligned $< 2> $@ %.out32: % - $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr --misaligned $< 2> $@ define compile_template |