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| author | Andrew Waterman <andrew@sifive.com> | 2023-04-06 09:50:57 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-04-06 09:50:57 -0700 |
| commit | 385ca8fa6de6289ed26f85cde11cedcdb805c60e (patch) | |
| tree | 2568cb5ac53a9621a3f3b5f9270fd14f9e29add1 /isa | |
| parent | c825b1f1678be926b226c74a9ed997a4ea99db98 (diff) | |
| download | riscv-tests-385ca8fa6de6289ed26f85cde11cedcdb805c60e.zip riscv-tests-385ca8fa6de6289ed26f85cde11cedcdb805c60e.tar.gz riscv-tests-385ca8fa6de6289ed26f85cde11cedcdb805c60e.tar.bz2 | |
Include Zicntr in Spike ISA string
Spike no longer enables Zicntr by default, so turn it on explicitly.
cc @jerryz123
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/isa/Makefile b/isa/Makefile index c542f33..d66b901 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -50,10 +50,10 @@ vpath %.S $(src_dir) $(RISCV_OBJDUMP) $< > $@ %.out: % - $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr --misaligned $< 2> $@ %.out32: % - $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot --misaligned $< 2> $@ + $(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr --misaligned $< 2> $@ define compile_template |