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2020-02-14rvv: fix Vxrm not reflected in fcsrDave.Wen1-2/+7
2020-02-13Merge branch 'avpatel-linux_boot_v1'Andrew Waterman5-5/+56
2020-02-14Make spike capable of booting LinuxAnup Patel5-5/+56
2020-02-12Improve --varch error checking. (#394)Tim Newsome3-12/+22
2020-02-11Merge pull request #393 from riscv/fesvr-dmactive-before-readAndrew Waterman1-3/+3
2020-02-11FESVR: ensure dmactive is 1 before reading debug module registersMegan Wachs1-3/+3
2020-02-10Merge pull request #392 from riscv/fesvr-no-dm-when-dmactive-0Andrew Waterman1-1/+1
2020-02-10FESVR: Can't read a DM register when DMACTIVE=0Megan Wachs1-1/+1
2020-02-06Fix incorrect commentsAndrew Waterman2-2/+2
2020-02-05Fix immediate signedness in vector disassemblyAndrew Waterman1-3/+3
2020-01-31Merge pull request #390 from jrtc27/payloadAndrew Waterman2-8/+37
2020-01-31Support loading multiple ELF files via a new payload HTIF optionJames Clarke2-7/+31
2020-01-31Support plusarg +h/+help option for HTIFJames Clarke2-1/+6
2020-01-30Fix pmpcfg0 initial value regression from cb254bfab5fbb6d69e5dd336798861e7c11...Andrew Waterman1-5/+5
2020-01-29Initialize PMPs with set_csr to fix WARLness of initial valueAndrew Waterman1-3/+6
2020-01-25Allow EM_NONE ELFs, tooAndrew Waterman2-1/+3
2020-01-25Refuse to load non-EXEC/non-RISC-V/non-V1 ELFs (#388)Alexander Lent2-0/+10
2020-01-24Prevent pmpaddr* and satp from holding invalid physical addressesAndrew Waterman1-2/+3
2020-01-24Merge pull request #387 from chihminchao/rvv-fixAndrew Waterman3-56/+2
2020-01-24rvv: fix corner case when input are 1's and shift amount is maximumChih-Min Chao2-2/+2
2020-01-24rvv: remove duplicate vectorUnit declarationChih-Min Chao1-54/+0
2020-01-22Merge pull request #383 from chihminchao/rvv-commitlogAndrew Waterman27-143/+291
2020-01-22commitlog: rvv: add commitlog support to misc instrutionsChih-Min Chao7-16/+16
2020-01-22commitlog: rvv: add commitlog support to integer instructionsChih-Min Chao2-37/+37
2020-01-22commitlog: rvv: add commitlog support to float instrunctionsChih-Min Chao15-31/+30
2020-01-22commitlog: rvv: add commitlog support to load instructionsChih-Min Chao1-8/+9
2020-01-22commitlog: rvv: change vector register read/write interfaceChih-Min Chao3-2/+65
2020-01-22commitlog: extend reg record to keep multiple accesssChih-Min Chao4-23/+61
2020-01-13commitlog: extend load/store record to keep multiple accessChih-Min Chao4-24/+17
2020-01-13state: rewrite state_t initializationChih-Min Chao2-5/+59
2020-01-13Make minimum RTI behavior more realistic. (#375)Tim Newsome1-32/+35
2020-01-13Expose sstatus.vs fieldAndrew Waterman1-0/+1
2020-01-13Merge pull request #378 from chihminchao/rvv-0.8-float64Andrew Waterman85-109/+458
2020-01-13doc: update vector extension versionChih-Min Chao1-1/+1
2020-01-13rvv: segment load/store needs to check destination rangeChih-Min Chao1-2/+3
2020-01-13rvv: add vmv[1248]r.vChih-Min Chao9-6/+45
2020-01-13rvv: fix vfwcvt/vfncvt for f32 -> f64 and f64 -> f32Chih-Min Chao13-25/+60
2020-01-09Decouple spike-dasm program from simulator codeAndrew Waterman1-4/+21
2020-01-09rvv: refinve vfmv to support float64Chih-Min Chao4-29/+62
2020-01-09rvv: add vfredxxx.vs and vfwred[o]sum.vs float64 supportChih-Min Chao7-12/+48
2020-01-09rvv: add vmfxxx.v[vf] float64 supportChih-Min Chao11-26/+85
2020-01-09rvv: add vfxxx.vf float64 supportChih-Min Chao23-3/+79
2020-01-09rvv: add vfxxx.vv float64 suuportChih-Min Chao22-5/+75
2019-12-20Merge pull request #366 from chihminchao/rvv-0.8-draft-20191118Andrew Waterman81-389/+554
2019-12-20rvv: support new mstatus.vs field defined in v0.8Chih-Min Chao4-15/+38
2019-12-20rvv: refine fault-first loopChih-Min Chao1-2/+1
2019-12-20rvv: make vlx/vsx match 0.8 specChih-Min Chao12-42/+49
2019-12-20rvv: change vmerge/vslideup register checking ruleChih-Min Chao7-3/+7
2019-12-20rvv: change vsetvl[i] to match 0.8 specChih-Min Chao4-8/+8
2019-12-20rvv: remove unsupported widen sewChih-Min Chao1-6/+0
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