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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-12-20 10:14:23 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-12-20 10:18:01 -0800 |
| commit | b812e15a8c95c4b2bb22b053efaf922b796245e4 (patch) | |
| tree | f68fba2a9e1cec4a2c671665aba90f025cbd016a | |
| parent | b4a5a1b34483cdf5c5041762dac070cfcad562c1 (diff) | |
| download | riscv-isa-sim-b812e15a8c95c4b2bb22b053efaf922b796245e4.zip riscv-isa-sim-b812e15a8c95c4b2bb22b053efaf922b796245e4.tar.gz riscv-isa-sim-b812e15a8c95c4b2bb22b053efaf922b796245e4.tar.bz2 | |
rvv: refine fault-first loop
This replaces loop boudary (vlmax) by vl.
In origin, vlmax boundary is used for tail-zero.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/decode.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 5d8cf6d..1750121 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1532,10 +1532,9 @@ for (reg_t i = 0; i < vlmax; ++i) { \ const reg_t baseAddr = RS1; \ const reg_t rd_num = insn.rd(); \ bool early_stop = false; \ - const reg_t vlmax = P.VU.vlmax; \ const reg_t vlmul = P.VU.vlmul; \ p->VU.vstart = 0; \ - for (reg_t i = 0; i < vlmax && vl != 0; ++i) { \ + for (reg_t i = 0; i < vl; ++i) { \ VI_STRIP(i); \ VI_ELEMENT_SKIP(i); \ \ |