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| author | Andrew Waterman <andrew@sifive.com> | 2020-01-29 20:13:23 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-01-29 20:13:23 -0800 |
| commit | cb254bfab5fbb6d69e5dd336798861e7c1183e52 (patch) | |
| tree | fd0378f587e6ecd91901565e93ccd7dcab194eea | |
| parent | 81cf0fae1d749d1828ecf0cba9ae31f5d31b7ece (diff) | |
| download | riscv-isa-sim-cb254bfab5fbb6d69e5dd336798861e7c1183e52.zip riscv-isa-sim-cb254bfab5fbb6d69e5dd336798861e7c1183e52.tar.gz riscv-isa-sim-cb254bfab5fbb6d69e5dd336798861e7c1183e52.tar.bz2 | |
Initialize PMPs with set_csr to fix WARLness of initial value
| -rw-r--r-- | riscv/processor.cc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index fb7476b..b34eb5c 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -254,10 +254,7 @@ void state_t::reset(reg_t max_isa) debug_mode = false; memset(this->pmpcfg, 0, sizeof(this->pmpcfg)); - pmpcfg[0] = PMP_R | PMP_W | PMP_X | PMP_NAPOT; - memset(this->pmpaddr, 0, sizeof(this->pmpaddr)); - pmpaddr[0] = ~reg_t(0); fflags = 0; frm = 0; @@ -351,6 +348,12 @@ void processor_t::set_log_commits(bool value) void processor_t::reset() { state.reset(max_isa); + + // For backwards compatibility with software that is unaware of PMP, + // initialize PMP to permit unprivileged access to all of memory. + set_csr(CSR_PMPADDR0, ~reg_t(0)); + set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT); + state.dcsr.halt = halt_on_reset; halt_on_reset = false; set_csr(CSR_MSTATUS, state.mstatus); |