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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-01-06 20:15:34 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-01-22 07:54:18 -0800 |
| commit | e1cb87f7d7626d749c687020c095f17c31858592 (patch) | |
| tree | ca5545d086a03176ec997b6134ee217dc9ddc3df | |
| parent | 4a6b6946bddd6569cc1086acee528b981fc08b93 (diff) | |
| download | riscv-isa-sim-e1cb87f7d7626d749c687020c095f17c31858592.zip riscv-isa-sim-e1cb87f7d7626d749c687020c095f17c31858592.tar.gz riscv-isa-sim-e1cb87f7d7626d749c687020c095f17c31858592.tar.bz2 | |
commitlog: rvv: add commitlog support to load instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/decode.h | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index a571efd..8999d93 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1519,16 +1519,17 @@ for (reg_t i = 0; i < vlmax; ++i) { \ ld_width##_t val = MMU.load_##ld_width(baseAddr + (stride) + (offset) * elt_byte); \ switch(P.VU.vsew){ \ case e8: \ - P.VU.elt<uint8_t>(vd + fn * vlmul, vreg_inx) = val; \ + P.VU.elt<uint8_t>(vd + fn * vlmul, vreg_inx, true) = val; \ break; \ case e16: \ - P.VU.elt<uint16_t>(vd + fn * vlmul, vreg_inx) = val; \ + P.VU.elt<uint16_t>(vd + fn * vlmul, vreg_inx, true) = val; \ break; \ case e32: \ - P.VU.elt<uint32_t>(vd + fn * vlmul, vreg_inx) = val; \ + P.VU.elt<uint32_t>(vd + fn * vlmul, vreg_inx, true) = val; \ break; \ default: \ - P.VU.elt<uint64_t>(vd + fn * vlmul, vreg_inx) = val; \ + P.VU.elt<uint64_t>(vd + fn * vlmul, vreg_inx, true) = val; \ + break; \ } \ } \ } \ @@ -1582,16 +1583,16 @@ for (reg_t i = 0; i < vlmax; ++i) { \ \ switch (sew) { \ case e8: \ - p->VU.elt<uint8_t>(rd_num + fn * vlmul, vreg_inx) = val; \ + p->VU.elt<uint8_t>(rd_num + fn * vlmul, vreg_inx, true) = val; \ break; \ case e16: \ - p->VU.elt<uint16_t>(rd_num + fn * vlmul, vreg_inx) = val; \ + p->VU.elt<uint16_t>(rd_num + fn * vlmul, vreg_inx, true) = val; \ break; \ case e32: \ - p->VU.elt<uint32_t>(rd_num + fn * vlmul, vreg_inx) = val; \ + p->VU.elt<uint32_t>(rd_num + fn * vlmul, vreg_inx, true) = val; \ break; \ case e64: \ - p->VU.elt<uint64_t>(rd_num + fn * vlmul, vreg_inx) = val; \ + p->VU.elt<uint64_t>(rd_num + fn * vlmul, vreg_inx, true) = val; \ break; \ } \ } \ |