Merge pull request #387 from chihminchao/rvv-fix

Rvv fix

3 files changed, 2 insertions, 56 deletions

diff --git a/riscv/insns/vnclipu_wi.h b/riscv/insns/vnclipu_wi.h
index b1527f7..e24aec1 100644
--- a/riscv/insns/vnclipu_wi.h
+++ b/riscv/insns/vnclipu_wi.h
@@ -3,7 +3,7 @@ VRM xrm = P.VU.get_vround_mode();
 uint64_t int_max = ~(-1ll << P.VU.vsew);
 VI_VVXI_LOOP_NARROW
 ({
-  uint64_t result = vs2_u;
+  uint128_t result = vs2_u;
   unsigned shift = zimm5 & ((sew * 2) - 1);
 
   // rounding
diff --git a/riscv/insns/vssrl_vi.h b/riscv/insns/vssrl_vi.h
index bf554ca..55e085d 100644
--- a/riscv/insns/vssrl_vi.h
+++ b/riscv/insns/vssrl_vi.h
@@ -3,7 +3,7 @@ VRM xrm = P.VU.get_vround_mode();
 VI_VI_ULOOP
 ({
   int sh = simm5 & (sew - 1) & 0x1f;
-  uint64_t val = vs2;
+  uint128_t val = vs2;
 
   INT_ROUNDING(val, xrm, sh);
   vd = val >> sh;
diff --git a/riscv/processor.h b/riscv/processor.h
index b0f639f..63c885b 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -151,60 +151,6 @@ struct type_sew_t<64>
   using type=int64_t;
 };
 
-class vectorUnit_t {
-  public:
-    processor_t* p;
-    void *reg_file;
-    char reg_referenced[NVPR];
-    int setvl_count;
-    reg_t reg_mask, vlmax, vmlen;
-    reg_t vstart, vxrm, vxsat, vl, vtype, vlenb;
-    reg_t vediv, vsew, vlmul;
-    reg_t ELEN, VLEN, SLEN;
-    bool vill;
-
-    // vector element for varies SEW
-    template<class T>
-      T& elt(reg_t vReg, reg_t n){
-        assert(vsew != 0);
-        assert((VLEN >> 3)/sizeof(T) > 0);
-        reg_t elts_per_reg = (VLEN >> 3) / (sizeof(T));
-        vReg += n / elts_per_reg;
-        n = n % elts_per_reg;
-#ifdef WORDS_BIGENDIAN
-	// "V" spec 0.7.1 requires lower indices to map to lower significant
-	// bits when changing SEW, thus we need to index from the end on BE.
-	n ^= elts_per_reg - 1;
-#endif
-        reg_referenced[vReg] = 1;
-
-        T *regStart = (T*)((char*)reg_file + vReg * (VLEN >> 3));
-        return regStart[n];
-      }
-  public:
-
-    void reset();
-
-    vectorUnit_t(){
-      reg_file = 0;
-    }
-
-    ~vectorUnit_t(){
-      free(reg_file);
-      reg_file = 0;
-    }
-
-    reg_t set_vl(int rd, int rs1, reg_t reqVL, reg_t newType);
-
-    reg_t get_vlen() { return VLEN; }
-    reg_t get_elen() { return ELEN; }
-    reg_t get_slen() { return SLEN; }
-
-    VRM get_vround_mode() {
-      return (VRM)vxrm;
-    }
-};
-
 // architectural state of a RISC-V hart
 struct state_t
 {