rvv: add vmv[1248]r.v

simple register copy instructions

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

9 files changed, 45 insertions, 6 deletions

diff --git a/riscv/encoding.h b/riscv/encoding.h
index 6d691e7..26142db 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -1266,6 +1266,14 @@
 #define MASK_VSADD_VI  0xfc00707f
 #define MATCH_VSLL_VI 0x94003057
 #define MASK_VSLL_VI  0xfc00707f
+#define MATCH_VMV1R_V 0x9e003057
+#define MASK_VMV1R_V  0xfe0ff07f
+#define MATCH_VMV2R_V 0x9e00b057
+#define MASK_VMV2R_V  0xfe0ff07f
+#define MATCH_VMV4R_V 0x9e01b057
+#define MASK_VMV4R_V  0xfe0ff07f
+#define MATCH_VMV8R_V 0x9e03b057
+#define MASK_VMV8R_V  0xfe0ff07f
 #define MATCH_VSRL_VI 0xa0003057
 #define MASK_VSRL_VI  0xfc00707f
 #define MATCH_VSRA_VI 0xa4003057
@@ -2305,6 +2313,10 @@ DECLARE_INSN(vmsgt_vi, MATCH_VMSGT_VI, MASK_VMSGT_VI)
 DECLARE_INSN(vsaddu_vi, MATCH_VSADDU_VI, MASK_VSADDU_VI)
 DECLARE_INSN(vsadd_vi, MATCH_VSADD_VI, MASK_VSADD_VI)
 DECLARE_INSN(vsll_vi, MATCH_VSLL_VI, MASK_VSLL_VI)
+DECLARE_INSN(vmv1r_v, MATCH_VMV1R_V, MASK_VMV1R_V)
+DECLARE_INSN(vmv2r_v, MATCH_VMV2R_V, MASK_VMV2R_V)
+DECLARE_INSN(vmv4r_v, MATCH_VMV4R_V, MASK_VMV4R_V)
+DECLARE_INSN(vmv8r_v, MATCH_VMV8R_V, MASK_VMV8R_V)
 DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI)
 DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI)
 DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI)
diff --git a/riscv/insns/vl1r_v.h b/riscv/insns/vl1r_v.h
index 8dabcb6..eded573 100644
--- a/riscv/insns/vl1r_v.h
+++ b/riscv/insns/vl1r_v.h
@@ -3,9 +3,7 @@ require_vector;
 const reg_t baseAddr = RS1;
 const reg_t vd = insn.rd();
 for (reg_t i = 0; i < P.VU.vlenb; ++i) {
-  
   auto val = MMU.load_uint8(baseAddr + i);
-  fprintf(stderr, "here: %ld: %x\n", i, val);
   P.VU.elt<uint8_t>(vd, i) = val;
 }
 P.VU.vstart = 0;
diff --git a/riscv/insns/vmv1r_v.h b/riscv/insns/vmv1r_v.h
new file mode 100644
index 0000000..bbdeab9
--- /dev/null
+++ b/riscv/insns/vmv1r_v.h
@@ -0,0 +1,2 @@
+// vmv1r.v vd, vs2
+#include "vmvnfr_v.h"
diff --git a/riscv/insns/vmv2r_v.h b/riscv/insns/vmv2r_v.h
new file mode 100644
index 0000000..1ac8e09
--- /dev/null
+++ b/riscv/insns/vmv2r_v.h
@@ -0,0 +1,2 @@
+// vmv2r.v vd, vs2
+#include "vmvnfr_v.h"
diff --git a/riscv/insns/vmv4r_v.h b/riscv/insns/vmv4r_v.h
new file mode 100644
index 0000000..2068731
--- /dev/null
+++ b/riscv/insns/vmv4r_v.h
@@ -0,0 +1,2 @@
+// vmv4r.v vd, vs2
+#include "vmvnfr_v.h"
diff --git a/riscv/insns/vmv8r_v.h b/riscv/insns/vmv8r_v.h
new file mode 100644
index 0000000..2b205fc
--- /dev/null
+++ b/riscv/insns/vmv8r_v.h
@@ -0,0 +1,2 @@
+// vmv8r.v vd, vs2
+#include "vmvnfr_v.h"
diff --git a/riscv/insns/vmvnfr_v.h b/riscv/insns/vmvnfr_v.h
new file mode 100644
index 0000000..6ae66d5
--- /dev/null
+++ b/riscv/insns/vmvnfr_v.h
@@ -0,0 +1,12 @@
+// vmv1r.v vd, vs2
+require_vector;
+const reg_t baseAddr = RS1;
+const reg_t vd = insn.rd();
+const reg_t vs2 = insn.rs2();
+const reg_t len = insn.rs1() + 1;
+require((vd & (len - 1)) == 0);
+require((vs2 & (len - 1)) == 0);
+if (vd != vs2)
+  memcpy(&P.VU.elt<uint8_t>(vd, 0),
+         &P.VU.elt<uint8_t>(vs2, 0), P.VU.vlenb * len);
+P.VU.vstart = 0;
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index db1bdcc..252b196 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -384,6 +384,10 @@ riscv_insn_ext_v_alu_int = \
 	vmv_v_v \
 	vmv_v_x \
 	vmv_x_s \
+	vmv1r_v \
+	vmv2r_v \
+	vmv4r_v \
+	vmv8r_v \
 	vmxnor_mm \
 	vmxor_mm \
 	vnclip_wi \
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc
index 5ecad58..addc223 100644
--- a/spike_main/disasm.cc
+++ b/spike_main/disasm.cc
@@ -911,10 +911,10 @@ disassembler_t::disassembler_t(int xlen)
   DISASM_OPIV_VX__INSN(vssubu,    0);
   DISASM_OPIV_VX__INSN(vssub,     1);
   DISASM_OPIV_VXI_INSN(vsll,      1, v);
-  DISASM_OPIV_VX__INSN(vaaddu,    0);
-  DISASM_OPIV_VX__INSN(vaadd,     0);
-  DISASM_OPIV_VX__INSN(vasubu,    0);
-  DISASM_OPIV_VX__INSN(vasub,     0);
+  DISASM_INSN("vmv1r.v", vmv1r_v, 0, {&vd, &vs2});
+  DISASM_INSN("vmv2r.v", vmv2r_v, 0, {&vd, &vs2});
+  DISASM_INSN("vmv4r.v", vmv4r_v, 0, {&vd, &vs2});
+  DISASM_INSN("vmv8r.v", vmv8r_v, 0, {&vd, &vs2});
   DISASM_OPIV_VX__INSN(vsmul,     1);
   DISASM_OPIV_VXI_INSN(vsrl,      0, v);
   DISASM_OPIV_VXI_INSN(vsra,      0, v);
@@ -937,6 +937,11 @@ disassembler_t::disassembler_t(int xlen)
 
   //OPMVV/OPMVX
   //0b00_0000
+  DISASM_OPIV_VX__INSN(vaaddu,    0);
+  DISASM_OPIV_VX__INSN(vaadd,     0);
+  DISASM_OPIV_VX__INSN(vasubu,    0);
+  DISASM_OPIV_VX__INSN(vasub,     0);
+
   DISASM_OPIV_S___INSN(vredsum,   1);
   DISASM_OPIV_S___INSN(vredand,   1);
   DISASM_OPIV_S___INSN(vredor,    1);