commitlog: rvv: add commitlog support to misc instrutions

other instructions, which doesn't use macro in decoder.h

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

7 files changed, 16 insertions, 16 deletions

diff --git a/riscv/insns/vcompress_vm.h b/riscv/insns/vcompress_vm.h
index 77e91bf..2efb99d 100644
--- a/riscv/insns/vcompress_vm.h
+++ b/riscv/insns/vcompress_vm.h
@@ -16,16 +16,16 @@ VI_GENERAL_LOOP_BASE
   if (do_mask) {
     switch (sew) {
     case e8:
-      P.VU.elt<uint8_t>(rd_num, pos) = P.VU.elt<uint8_t>(rs2_num, i);
+      P.VU.elt<uint8_t>(rd_num, pos, true) = P.VU.elt<uint8_t>(rs2_num, i);
       break;
     case e16:
-      P.VU.elt<uint16_t>(rd_num, pos) = P.VU.elt<uint16_t>(rs2_num, i);
+      P.VU.elt<uint16_t>(rd_num, pos, true) = P.VU.elt<uint16_t>(rs2_num, i);
       break;
     case e32:
-      P.VU.elt<uint32_t>(rd_num, pos) = P.VU.elt<uint32_t>(rs2_num, i);
+      P.VU.elt<uint32_t>(rd_num, pos, true) = P.VU.elt<uint32_t>(rs2_num, i);
       break;
     default:
-      P.VU.elt<uint64_t>(rd_num, pos) = P.VU.elt<uint64_t>(rs2_num, i);
+      P.VU.elt<uint64_t>(rd_num, pos, true) = P.VU.elt<uint64_t>(rs2_num, i);
       break;
     }
 
diff --git a/riscv/insns/vid_v.h b/riscv/insns/vid_v.h
index 25422d6..97a0049 100644
--- a/riscv/insns/vid_v.h
+++ b/riscv/insns/vid_v.h
@@ -15,16 +15,16 @@ for (reg_t i = P.VU.vstart ; i < P.VU.vl; ++i) {
 
   switch (sew) {
   case e8:
-    P.VU.elt<uint8_t>(rd_num, i) = i;
+    P.VU.elt<uint8_t>(rd_num, i, true) = i;
     break;
   case e16:
-    P.VU.elt<uint16_t>(rd_num, i) = i;
+    P.VU.elt<uint16_t>(rd_num, i, true) = i;
     break;
   case e32:
-    P.VU.elt<uint32_t>(rd_num, i) = i;
+    P.VU.elt<uint32_t>(rd_num, i, true) = i;
     break;
   default:
-    P.VU.elt<uint64_t>(rd_num, i) = i;
+    P.VU.elt<uint64_t>(rd_num, i, true) = i;
     break;
   }
 }
diff --git a/riscv/insns/viota_m.h b/riscv/insns/viota_m.h
index 04bfcd8..f0ef62a 100644
--- a/riscv/insns/viota_m.h
+++ b/riscv/insns/viota_m.h
@@ -31,19 +31,19 @@ for (reg_t i = 0; i < vl; ++i) {
   bool use_ori = (insn.v_vm() == 0) && !do_mask;
   switch (sew) {
   case e8:
-    P.VU.elt<uint8_t>(rd_num, i) = use_ori ?
+    P.VU.elt<uint8_t>(rd_num, i, true) = use_ori ?
                                    P.VU.elt<uint8_t>(rd_num, i) : cnt;
     break;
   case e16:
-    P.VU.elt<uint16_t>(rd_num, i) = use_ori ?
+    P.VU.elt<uint16_t>(rd_num, i, true) = use_ori ?
                                     P.VU.elt<uint16_t>(rd_num, i) : cnt;
     break;
   case e32:
-    P.VU.elt<uint32_t>(rd_num, i) = use_ori ?
+    P.VU.elt<uint32_t>(rd_num, i, true) = use_ori ?
                                     P.VU.elt<uint32_t>(rd_num, i) : cnt;
     break;
   default:
-    P.VU.elt<uint64_t>(rd_num, i) = use_ori ?
+    P.VU.elt<uint64_t>(rd_num, i, true) = use_ori ?
                                     P.VU.elt<uint64_t>(rd_num, i) : cnt;
     break;
   }
diff --git a/riscv/insns/vl1r_v.h b/riscv/insns/vl1r_v.h
index eded573..09f4040 100644
--- a/riscv/insns/vl1r_v.h
+++ b/riscv/insns/vl1r_v.h
@@ -4,6 +4,6 @@ const reg_t baseAddr = RS1;
 const reg_t vd = insn.rd();
 for (reg_t i = 0; i < P.VU.vlenb; ++i) {
   auto val = MMU.load_uint8(baseAddr + i);
-  P.VU.elt<uint8_t>(vd, i) = val;
+  P.VU.elt<uint8_t>(vd, i, true) = val;
 }
 P.VU.vstart = 0;
diff --git a/riscv/insns/vmsbf_m.h b/riscv/insns/vmsbf_m.h
index 443fcbb..fd352ea 100644
--- a/riscv/insns/vmsbf_m.h
+++ b/riscv/insns/vmsbf_m.h
@@ -16,10 +16,10 @@ for (reg_t i = P.VU.vstart; i < vl; ++i) {
 
   bool vs2_lsb = ((P.VU.elt<uint64_t>(rs2_num, midx) >> mpos) & 0x1) == 1;
   bool do_mask = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1;
-  auto &vd = P.VU.elt<uint64_t>(rd_num, midx);
 
 
   if (insn.v_vm() == 1 || (insn.v_vm() == 0 && do_mask)) {
+    auto &vd = P.VU.elt<uint64_t>(rd_num, midx, true);
     uint64_t res = 0;
     if (!has_one && !vs2_lsb) {
       res = 1;
diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h
index 381088b..0896095 100644
--- a/riscv/insns/vmsif_m.h
+++ b/riscv/insns/vmsif_m.h
@@ -16,9 +16,9 @@ for (reg_t i = P.VU.vstart ; i < vl; ++i) {
 
   bool vs2_lsb = ((P.VU.elt<uint64_t>(rs2_num, midx ) >> mpos) & 0x1) == 1;
   bool do_mask = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1;
-  auto &vd = P.VU.elt<uint64_t>(rd_num, midx);
 
   if (insn.v_vm() == 1 || (insn.v_vm() == 0 && do_mask)) {
+    auto &vd = P.VU.elt<uint64_t>(rd_num, midx, true);
     uint64_t res = 0;
     if (!has_one && !vs2_lsb) {
       res = 1;
diff --git a/riscv/insns/vmsof_m.h b/riscv/insns/vmsof_m.h
index d66002d..26a89f0 100644
--- a/riscv/insns/vmsof_m.h
+++ b/riscv/insns/vmsof_m.h
@@ -16,9 +16,9 @@ for (reg_t i = P.VU.vstart ; i < vl; ++i) {
 
   bool vs2_lsb = ((P.VU.elt<uint64_t>(rs2_num, midx ) >> mpos) & 0x1) == 1;
   bool do_mask = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1;
-  uint64_t &vd = P.VU.elt<uint64_t>(rd_num, midx);
 
   if (insn.v_vm() == 1 || (insn.v_vm() == 0 && do_mask)) {
+    uint64_t &vd = P.VU.elt<uint64_t>(rd_num, midx, true);
     uint64_t res = 0;
     if(!has_one && vs2_lsb) {
       has_one = true;