rvv: make vlx/vsx match 0.8 spec

1. make offset unsigned
2. refine checking rule

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

12 files changed, 49 insertions, 42 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index 0d79e71..5d8cf6d 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -385,6 +385,15 @@ static inline bool is_overlapped(const int astart, const int asize,
   if (insn.v_vm() == 0) \
     require(insn.rd() != 0);
 
+#define VI_CHECK_LDST_INDEX \
+  require_vector; \
+  require((insn.rd() & (P.VU.vlmul - 1)) == 0); \
+  require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \
+  if (insn.v_nf() > 0) \
+    require(!is_overlapped(insn.rd(), P.VU.vlmul, insn.rs2(), P.VU.vlmul)); \
+  if (insn.v_vm() == 0 && (insn.v_nf() > 0 || P.VU.vlmul > 1)) \
+    require(insn.rd() != 0); \
+
 #define VI_CHECK_MSS(is_vs1) \
   if (P.VU.vlmul > 1) { \
     require(!is_overlapped(insn.rd(), 1, insn.rs2(), P.VU.vlmul)); \
@@ -1419,31 +1428,29 @@ reg_t index[vlmax]; \
 for (reg_t i = 0; i < vlmax; ++i) { \
   switch(P.VU.vsew) { \
     case e8: \
-      index[i] = P.VU.elt<int8_t>(v, i); \
+      index[i] = P.VU.elt<uint8_t>(v, i); \
       break; \
     case e16: \
-      index[i] = P.VU.elt<int16_t>(v, i); \
+      index[i] = P.VU.elt<uint16_t>(v, i); \
       break; \
     case e32: \
-      index[i] = P.VU.elt<int32_t>(v, i); \
+      index[i] = P.VU.elt<uint32_t>(v, i); \
       break; \
     case e64: \
-      index[i] = P.VU.elt<int64_t>(v, i); \
+      index[i] = P.VU.elt<uint64_t>(v, i); \
       break; \
   } \
 }
 
-#define VI_ST(stride, offset, st_width, elt_byte) \
+#define VI_ST_COMMON(stride, offset, st_width, elt_byte) \
   const reg_t nf = insn.v_nf() + 1; \
   require((nf * P.VU.vlmul) <= (NVPR / 4)); \
-  VI_CHECK_SXX; \
   const reg_t vl = P.VU.vl; \
   const reg_t baseAddr = RS1; \
   const reg_t vs3 = insn.rd(); \
   require(vs3 + nf <= NVPR); \
-  const reg_t vlmax = P.VU.vlmax; \
   const reg_t vlmul = P.VU.vlmul; \
-  for (reg_t i = 0; i < vlmax && vl != 0; ++i) { \
+  for (reg_t i = 0; i < vl; ++i) { \
     VI_STRIP(i) \
     VI_ELEMENT_SKIP(i); \
     P.VU.vstart = i; \
@@ -1468,17 +1475,15 @@ for (reg_t i = 0; i < vlmax; ++i) { \
   } \
   P.VU.vstart = 0; 
 
-#define VI_LD(stride, offset, ld_width, elt_byte) \
+#define VI_LD_COMMON(stride, offset, ld_width, elt_byte) \
   const reg_t nf = insn.v_nf() + 1; \
   require((nf * P.VU.vlmul) <= (NVPR / 4)); \
-  VI_CHECK_SXX; \
   const reg_t vl = P.VU.vl; \
   const reg_t baseAddr = RS1; \
   const reg_t vd = insn.rd(); \
   require(vd + nf <= NVPR); \
-  const reg_t vlmax = P.VU.vlmax; \
   const reg_t vlmul = P.VU.vlmul; \
-  for (reg_t i = 0; i < vlmax && vl != 0; ++i) { \
+  for (reg_t i = 0; i < vl; ++i) { \
     VI_ELEMENT_SKIP(i); \
     VI_STRIP(i); \
     P.VU.vstart = i; \
@@ -1501,6 +1506,21 @@ for (reg_t i = 0; i < vlmax; ++i) { \
   } \
   P.VU.vstart = 0;
 
+#define VI_LD(stride, offset, ld_width, elt_byte) \
+  VI_CHECK_SXX; \
+  VI_LD_COMMON(stride, offset, ld_width, elt_byte)
+
+#define VI_LD_INDEX(stride, offset, ld_width, elt_byte) \
+  VI_CHECK_LDST_INDEX; \
+  VI_LD_COMMON(stride, offset, ld_width, elt_byte)
+
+#define VI_ST(stride, offset, st_width, elt_byte) \
+  VI_CHECK_SXX; \
+  VI_ST_COMMON(stride, offset, st_width, elt_byte) \
+
+#define VI_ST_INDEX(stride, offset, st_width, elt_byte) \
+  VI_CHECK_LDST_INDEX; \
+  VI_ST_COMMON(stride, offset, st_width, elt_byte) \
 
 #define VI_LDST_FF(itype, tsew) \
   require(p->VU.vsew >= e##tsew && p->VU.vsew <= e64); \
diff --git a/riscv/insns/vlxb_v.h b/riscv/insns/vlxb_v.h
index 57ce8c8..768ecd3 100644
--- a/riscv/insns/vlxb_v.h
+++ b/riscv/insns/vlxb_v.h
@@ -1,5 +1,4 @@
 // vlxb.v and vlsseg[2-8]b.v
 require(P.VU.vsew >= e8);
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_LD(index[i], fn, int8, 1);
+VI_LD_INDEX(index[i], fn, int8, 1);
diff --git a/riscv/insns/vlxbu_v.h b/riscv/insns/vlxbu_v.h
index d8e3dd6..1bcd04c 100644
--- a/riscv/insns/vlxbu_v.h
+++ b/riscv/insns/vlxbu_v.h
@@ -1,5 +1,4 @@
 // vlxbu.v and vlxseg[2-8]bu.v
 require(P.VU.vsew >= e8);
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_LD(index[i], fn, uint8, 1);
+VI_LD_INDEX(index[i], fn, uint8, 1);
diff --git a/riscv/insns/vlxe_v.h b/riscv/insns/vlxe_v.h
index 1055eca..8035549 100644
--- a/riscv/insns/vlxe_v.h
+++ b/riscv/insns/vlxe_v.h
@@ -1,14 +1,12 @@
 // vlxe.v and vlxseg[2-8]e.v
 reg_t sew = P.VU.vsew;
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
 if (sew == e8) {
-  VI_LD(index[i], fn, int8, 1);
+  VI_LD_INDEX(index[i], fn, int8, 1);
 } else if (sew == e16) {
-  VI_LD(index[i], fn, int16, 2);
+  VI_LD_INDEX(index[i], fn, int16, 2);
 } else if (sew == e32) {
-  VI_LD(index[i], fn, int32, 4);
+  VI_LD_INDEX(index[i], fn, int32, 4);
 } else if (sew == e64) {
-  VI_LD(index[i], fn, int64, 8);
+  VI_LD_INDEX(index[i], fn, int64, 8);
 }
-
diff --git a/riscv/insns/vlxh_v.h b/riscv/insns/vlxh_v.h
index 9f4c3a1..e51b19f 100644
--- a/riscv/insns/vlxh_v.h
+++ b/riscv/insns/vlxh_v.h
@@ -1,5 +1,4 @@
 // vlxh.v and vlxseg[2-8]h.v
 require(P.VU.vsew >= e16);
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_LD(index[i], fn, int16, 2);
+VI_LD_INDEX(index[i], fn, int16, 2);
diff --git a/riscv/insns/vlxhu_v.h b/riscv/insns/vlxhu_v.h
index 9283127..1ca6171 100644
--- a/riscv/insns/vlxhu_v.h
+++ b/riscv/insns/vlxhu_v.h
@@ -1,5 +1,4 @@
 // vlxh.v and vlxseg[2-8]h.v
 require(P.VU.vsew >= e16);
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_LD(index[i], fn, uint16, 2);
+VI_LD_INDEX(index[i], fn, uint16, 2);
diff --git a/riscv/insns/vlxw_v.h b/riscv/insns/vlxw_v.h
index c1117a2..c2af748 100644
--- a/riscv/insns/vlxw_v.h
+++ b/riscv/insns/vlxw_v.h
@@ -1,6 +1,4 @@
 // vlxw.v and vlxseg[2-8]w.v
 require(P.VU.vsew >= e32);
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_LD(index[i], fn, int32, 4);
-
+VI_LD_INDEX(index[i], fn, int32, 4);
diff --git a/riscv/insns/vlxwu_v.h b/riscv/insns/vlxwu_v.h
index d3034bd..fb8dc11 100644
--- a/riscv/insns/vlxwu_v.h
+++ b/riscv/insns/vlxwu_v.h
@@ -1,5 +1,4 @@
 // vlxwu.v and vlxseg[2-8]wu.v
 require(P.VU.vsew >= e32);
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_LD(index[i], fn, uint32, 4);
+VI_LD_INDEX(index[i], fn, uint32, 4);
diff --git a/riscv/insns/vsxb_v.h b/riscv/insns/vsxb_v.h
index fb567fb..3ee421c 100644
--- a/riscv/insns/vsxb_v.h
+++ b/riscv/insns/vsxb_v.h
@@ -1,5 +1,4 @@
 // vsxb.v and vsxseg[2-8]b.v
 require(P.VU.vsew >= e8);
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_ST(index[i], fn, uint8, 1);
+VI_ST_INDEX(index[i], fn, uint8, 1);
diff --git a/riscv/insns/vsxe_v.h b/riscv/insns/vsxe_v.h
index 78c6605..8e5d6e7 100644
--- a/riscv/insns/vsxe_v.h
+++ b/riscv/insns/vsxe_v.h
@@ -1,15 +1,14 @@
 // vsxe.v and vsxseg[2-8]e.v
 reg_t sew = P.VU.vsew;
 require(sew >= e8 && sew <= e64);
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
 if (sew == e8) {
-  VI_ST(index[i], fn, uint8, 1);
+  VI_ST_INDEX(index[i], fn, uint8, 1);
 } else if (sew == e16) {
-  VI_ST(index[i], fn, uint16, 2);
+  VI_ST_INDEX(index[i], fn, uint16, 2);
 } else if (sew == e32) {
-  VI_ST(index[i], fn, uint32, 4);
+  VI_ST_INDEX(index[i], fn, uint32, 4);
 } else if (sew == e64) {
-  VI_ST(index[i], fn, uint64, 8);
+  VI_ST_INDEX(index[i], fn, uint64, 8);
 }
 
diff --git a/riscv/insns/vsxh_v.h b/riscv/insns/vsxh_v.h
index 6b0fcfd..8722fdc 100644
--- a/riscv/insns/vsxh_v.h
+++ b/riscv/insns/vsxh_v.h
@@ -1,5 +1,4 @@
 // vsxh.v and vsxseg[2-8]h.v
 require(P.VU.vsew >= e16);
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_ST(index[i], fn, uint16, 2);
+VI_ST_INDEX(index[i], fn, uint16, 2);
diff --git a/riscv/insns/vsxw_v.h b/riscv/insns/vsxw_v.h
index 2223d5b..a6d4046 100644
--- a/riscv/insns/vsxw_v.h
+++ b/riscv/insns/vsxw_v.h
@@ -1,5 +1,4 @@
 // vsxw.v and vsxseg[2-8]w.v
 require(P.VU.vsew >= e32);
-require((insn.rs2() & (P.VU.vlmul - 1)) == 0);
 VI_DUPLICATE_VREG(insn.rs2(), P.VU.vlmax);
-VI_ST(index[i], fn, uint32, 4);
+VI_ST_INDEX(index[i], fn, uint32, 4);