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| author | Andrew Waterman <andrew@sifive.com> | 2020-02-05 17:11:03 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-02-05 17:11:03 -0800 |
| commit | 2e60b8b06174771e1155f2dfe693cc49f8958def (patch) | |
| tree | 20444a731aa28651c5dcf9cbceedfc5b06809e75 | |
| parent | 39fd6f33e03540f25665cd99edd111ef1cf110b0 (diff) | |
| download | riscv-isa-sim-2e60b8b06174771e1155f2dfe693cc49f8958def.zip riscv-isa-sim-2e60b8b06174771e1155f2dfe693cc49f8958def.tar.gz riscv-isa-sim-2e60b8b06174771e1155f2dfe693cc49f8958def.tar.bz2 | |
Fix immediate signedness in vector disassembly
| -rw-r--r-- | spike_main/disasm.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index addc223..3951af5 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -884,8 +884,8 @@ disassembler_t::disassembler_t(int xlen) DISASM_OPIV_VXI_INSN(vor, 1, v); DISASM_OPIV_VXI_INSN(vxor, 1, v); DISASM_OPIV_VXI_INSN(vrgather, 0, v); - DISASM_OPIV__XI_INSN(vslideup, 1); - DISASM_OPIV__XI_INSN(vslidedown,1); + DISASM_OPIV__XI_INSN(vslideup, 0); + DISASM_OPIV__XI_INSN(vslidedown,0); //0b01_0000 DISASM_OPIV_VXIM_INSN(vadc, 1); @@ -923,7 +923,7 @@ disassembler_t::disassembler_t(int xlen) DISASM_OPIV_VXI_INSN(vnsrl, 0, w); DISASM_OPIV_VXI_INSN(vnsra, 0, w); DISASM_OPIV_VXI_INSN(vnclipu, 0, w); - DISASM_OPIV_VXI_INSN(vnclip, 1, w); + DISASM_OPIV_VXI_INSN(vnclip, 0, w); //0b11_0000 DISASM_OPIV_S___INSN(vwredsumu, 0); |