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2022-08-11Remove dead code in VI_VV_EXT macro (#1065)ksco1-3/+0
2022-08-10Merge pull request #1066 from plctlab/plct-nonfunc-fixAndrew Waterman59-170/+176
2022-08-10Add space between if/while/switch and '('Weiwei Li54-77/+77
2022-08-10Improve write log for vtype in set_vlWeiwei Li1-1/+2
2022-08-10Fix code indentation in processor.cc, interactive.cc, debug_module.h/ccWeiwei Li7-90/+90
2022-08-10Add missed decription for log-commits optionWeiwei Li1-0/+1
2022-08-10Fix description for mem related interactive commandsWeiwei Li1-4/+6
2022-08-10Add #ifdef RISCV_ENABLE_COMMITLOG for commitlog related codeWeiwei Li1-0/+2
2022-08-09Fix exception type for accessing (v)stimecmp (#1061)liweiwei901-6/+7
2022-08-08Merge pull request #831 from plctlab/plct-upstream-zfinxAndrew Waterman94-215/+289
2022-08-08Merge pull request #1059 from plctlab/plct-stateen-fixAndrew Waterman3-37/+21
2022-08-04Add stateen related check for float point instructionsWeiwei Li2-2/+3
2022-08-04 Add support for freg command to read X regs when enable Zfinxliweiwei3-13/+28
2022-08-04Modify F/D/Zfh instructions to add support for Zfinx/Zdinx/Zhinx{min} instruc...liweiwei89-197/+239
2022-08-04Add flags for Zfinx/Zdinx/Zhinx{min}liweiwei2-3/+19
2022-08-03Add Sstc support. (#1057)i2h26-5/+79
2022-08-03Fix exception type for accessing senvcfg/henvcfg/hstateenWeiwei Li1-6/+5
2022-08-03add stateen related check to frm/fflags and then apply to fcsr implicitlyWeiwei Li3-31/+16
2022-08-01Merge pull request #1055 from ctopal/umode_wfiAndrew Waterman1-1/+3
2022-08-01Merge pull request #1056 from riscv-software-src/debug_rom_buildAndrew Waterman2-5/+5
2022-08-01WFI condition fixCanberk Topal1-1/+3
2022-07-30DSCRATCH is now called DSCRATCH0Tim Newsome1-4/+4
2022-07-30Fix debug_rom.S build command error.Tim Newsome1-1/+1
2022-07-28Fix overflow issue of p-ext multiply instructions (#1053)ChunPing Chung8-8/+8
2022-07-26Add additional bits to medeleg (#1050)Brendan Sweeney1-0/+6
2022-07-25Pay attention to dmcs2.grouptype. (#1049)Tim Newsome1-1/+3
2022-07-21Merge pull request #1040 from plctlab/plct-priv-devAndrew Waterman5-31/+59
2022-07-21add base verify_permission in counter_proxy_csr_t::verify_permissionsWeiwei Li1-1/+3
2022-07-21add support for time/timeh/htimedelta/htimedeltah csrsWeiwei Li5-0/+49
2022-07-21modify minstret/mcycle/minstreth/mcycleh to reuse rv32_low/high_csr_tWeiwei Li3-44/+21
2022-07-18Fix load/store performance under clangAndrew Waterman2-2/+4
2022-07-18Merge pull request #1041 from plctlab/plct-new-csrsAndrew Waterman5-37/+44
2022-07-18Merge pull request #1047 from scottj97/fix-misaligned-hlvScott Johnson1-4/+19
2022-07-18Fix totally-broken misaligned HSVScott Johnson1-1/+5
2022-07-18Fix totally-broken misaligned HLV/HLVXScott Johnson1-1/+6
2022-07-18Remove no-longer-necessary typecastScott Johnson1-1/+1
2022-07-17modify the check for "state->prv >= PRV_M" to "state->prv == PRV_M"Weiwei Li1-1/+1
2022-07-17add U mode check for *envcfg*Weiwei Li1-24/+26
2022-07-17Fix the initial value and write mask for mstatusWeiwei Li1-2/+6
2022-07-17remove unnecessary ifdef for RISCV_ENABLE_DUAL_ENDIANWeiwei Li3-14/+0
2022-07-17extract the progress of computing the inital value of mstatus intoWeiwei Li2-9/+12
2022-07-15Split up misaligned store into several stepsScott Johnson1-2/+5
2022-07-15Split up misaligned load into several stepsScott Johnson1-2/+5
2022-07-15Merge pull request #1043 from YenHaoChen/pr-conditionalize-epmpAndrew Waterman4-0/+10
2022-07-14add support for mconfigptr csr: it's hardwired to zero currentlyWeiwei Li1-1/+1
2022-07-14add support for m/henvcfgh csrsWeiwei Li1-3/+15
2022-07-13Merge pull request #1045 from scottj97/fix1044Scott Johnson4-15/+62
2022-07-13Properly log mstatush side effect updatesScott Johnson3-2/+6
2022-07-13Add assertion to ensure proper logging of mstatus changes on RV32Scott Johnson1-0/+4
2022-07-13Use rv32_low_csr_t for Smstateen CSRsScott Johnson1-2/+8
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