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author | Scott Johnson <scott.johnson@arilinc.com> | 2022-07-13 10:21:43 -0700 |
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committer | Scott Johnson <scott.johnson@arilinc.com> | 2022-07-13 18:57:55 -0700 |
commit | b21a28bce174f2d1ac3e8a424bc9b9b1f01251a6 (patch) | |
tree | 4bfb4e372b7ab35c45aee1667a8b5202b38b09f9 | |
parent | f85b76edd00a529b3dbda88aee2802014c09de7d (diff) | |
download | riscv-isa-sim-b21a28bce174f2d1ac3e8a424bc9b9b1f01251a6.zip riscv-isa-sim-b21a28bce174f2d1ac3e8a424bc9b9b1f01251a6.tar.gz riscv-isa-sim-b21a28bce174f2d1ac3e8a424bc9b9b1f01251a6.tar.bz2 |
Add assertion to ensure proper logging of mstatus changes on RV32
-rw-r--r-- | riscv/csrs.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index dac3eef..7a52353 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -455,6 +455,10 @@ sstatus_proxy_csr_t::sstatus_proxy_csr_t(processor_t* const proc, const reg_t ad bool sstatus_proxy_csr_t::unlogged_write(const reg_t val) noexcept { const reg_t new_mstatus = (mstatus->read() & ~sstatus_write_mask) | (val & sstatus_write_mask); + // On RV32 this will only log the low 32 bits, so make sure we're + // not modifying anything in the upper 32 bits. + assert((sstatus_write_mask & 0xffffffffU) == sstatus_write_mask); + mstatus->write(new_mstatus); return false; // avoid double logging: already logged by mstatus->write() } |