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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-04 10:18:19 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-04 10:18:19 +0800 |
| commit | caee7f3fa508b0bf84eb3f8d60d6c9e43b0ccf61 (patch) | |
| tree | fe9b9bbfd16371e07586f58307d985188c301d59 | |
| parent | 8aaae32d1d8fc3d20d62aae3039d6591346e95de (diff) | |
| download | riscv-isa-sim-caee7f3fa508b0bf84eb3f8d60d6c9e43b0ccf61.zip riscv-isa-sim-caee7f3fa508b0bf84eb3f8d60d6c9e43b0ccf61.tar.gz riscv-isa-sim-caee7f3fa508b0bf84eb3f8d60d6c9e43b0ccf61.tar.bz2 | |
Add stateen related check for float point instructions
| -rw-r--r-- | riscv/csrs.cc | 2 | ||||
| -rw-r--r-- | riscv/decode.h | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index fc5dce1..7592c2d 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1201,7 +1201,7 @@ float_csr_t::float_csr_t(processor_t* const proc, const reg_t addr, const reg_t void float_csr_t::verify_permissions(insn_t insn, bool write) const { masked_csr_t::verify_permissions(insn, write); - require_fp; + require_fs; if (!proc->extension_enabled('F') && !proc->extension_enabled(EXT_ZFINX)) throw trap_illegal_instruction(insn.bits()); } diff --git a/riscv/decode.h b/riscv/decode.h index b5fad2d..850863f 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -292,7 +292,8 @@ do { \ #define require_extension(s) require(p->extension_enabled(s)) #define require_either_extension(A,B) require(p->extension_enabled(A) || p->extension_enabled(B)); #define require_impl(s) require(p->supports_impl(s)) -#define require_fp require(STATE.sstatus->enabled(SSTATUS_FS)) +#define require_fs require(STATE.sstatus->enabled(SSTATUS_FS)) +#define require_fp STATE.fflags->verify_permissions(insn, false) #define require_accelerator require(STATE.sstatus->enabled(SSTATUS_XS)) #define require_vector_vs require(STATE.sstatus->enabled(SSTATUS_VS)) #define require_vector(alu) \ |