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author | Scott Johnson <scott.johnson@arilinc.com> | 2022-07-13 10:45:41 -0700 |
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committer | Scott Johnson <scott.johnson@arilinc.com> | 2022-07-13 18:57:56 -0700 |
commit | 3688fd8302d1b7b8eea1dd8f6206ceab1bedfb2c (patch) | |
tree | 1a481ce817e2e5e2ecd4c9badb5cf2e1385bff00 | |
parent | b21a28bce174f2d1ac3e8a424bc9b9b1f01251a6 (diff) | |
download | riscv-isa-sim-3688fd8302d1b7b8eea1dd8f6206ceab1bedfb2c.zip riscv-isa-sim-3688fd8302d1b7b8eea1dd8f6206ceab1bedfb2c.tar.gz riscv-isa-sim-3688fd8302d1b7b8eea1dd8f6206ceab1bedfb2c.tar.bz2 |
Properly log mstatush side effect updates
These have never been logged properly.
-rw-r--r-- | riscv/csrs.cc | 4 | ||||
-rw-r--r-- | riscv/processor.cc | 3 | ||||
-rw-r--r-- | riscv/processor.h | 1 |
3 files changed, 6 insertions, 2 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 7a52353..6f8f260 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -616,7 +616,9 @@ bool misa_csr_t::unlogged_write(const reg_t val) noexcept { | (1 << CAUSE_STORE_GUEST_PAGE_FAULT) ; state->medeleg->write(state->medeleg->read() & ~hypervisor_exceptions); - state->mstatus->write(state->mstatus->read() & ~(MSTATUS_GVA | MSTATUS_MPV)); + const reg_t new_mstatus = state->mstatus->read() & ~(MSTATUS_GVA | MSTATUS_MPV); + state->mstatus->write(new_mstatus); + if (state->mstatush) state->mstatush->write(new_mstatus >> 32); // log mstatush change state->mie->write_with_mask(MIP_HS_MASK, 0); // also takes care of hie, sie state->mip->write_with_mask(MIP_HS_MASK, 0); // also takes care of hip, sip, hvip state->hstatus->write(0); diff --git a/riscv/processor.cc b/riscv/processor.cc index d431c68..8f77b47 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -193,7 +193,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) if (xlen == 32) { csrmap[CSR_MSTATUS] = std::make_shared<rv32_low_csr_t>(proc, CSR_MSTATUS, mstatus); - csrmap[CSR_MSTATUSH] = std::make_shared<rv32_high_csr_t>(proc, CSR_MSTATUSH, mstatus); + csrmap[CSR_MSTATUSH] = mstatush = std::make_shared<rv32_high_csr_t>(proc, CSR_MSTATUSH, mstatus); } else { csrmap[CSR_MSTATUS] = mstatus; } @@ -824,6 +824,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) s = set_field(s, MSTATUS_MPV, curr_virt); s = set_field(s, MSTATUS_GVA, t.has_gva()); state.mstatus->write(s); + if (state.mstatush) state.mstatush->write(s >> 32); // log mstatush change set_privilege(PRV_M); } } diff --git a/riscv/processor.h b/riscv/processor.h index 727c404..347ae16 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -133,6 +133,7 @@ struct state_t bool v; misa_csr_t_p misa; mstatus_csr_t_p mstatus; + csr_t_p mstatush; csr_t_p mepc; csr_t_p mtval; csr_t_p mtvec; |