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author | Scott Johnson <scott.johnson@arilinc.com> | 2022-07-15 18:20:52 -0700 |
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committer | Scott Johnson <scott.johnson@arilinc.com> | 2022-07-18 07:02:06 -0700 |
commit | 43ecb3424d68391e033f4df421c67c7f468fdff6 (patch) | |
tree | 9b2a347d0737a7b44eb328874b037e861f8072ae | |
parent | d61dceccdb43ae0025b3f02d825c3783e8ae10ea (diff) | |
download | riscv-isa-sim-43ecb3424d68391e033f4df421c67c7f468fdff6.zip riscv-isa-sim-43ecb3424d68391e033f4df421c67c7f468fdff6.tar.gz riscv-isa-sim-43ecb3424d68391e033f4df421c67c7f468fdff6.tar.bz2 |
Fix totally-broken misaligned HSV
It was accessing memory using the current privilege mode instead of
the expected guest privilege.
Once #872 is fixed, I suspect we can greatly simplify this.
-rw-r--r-- | riscv/mmu.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 70cb9e2..4e12805 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -78,7 +78,11 @@ public: for (size_t i = 0; i < size; i++) { const reg_t byteaddr = addr + (target_big_endian? size-1-i : i); const reg_t bytedata = data >> (i * 8); - store_uint8(byteaddr, bytedata, actually_store); + if (RISCV_XLATE_VIRT & xlate_flags) { + guest_store_uint8(byteaddr, bytedata, actually_store); + } else { + store_uint8(byteaddr, bytedata, actually_store); + } } #else bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags); |