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author | Andrew Waterman <andrew@sifive.com> | 2022-08-10 11:30:43 -0700 |
---|---|---|
committer | GitHub <noreply@github.com> | 2022-08-10 11:30:43 -0700 |
commit | 6dcef28ed23f26d8f57880a3763f7a85da9fd08b (patch) | |
tree | f5f5da62f53bced28e38349a1b41983bb916dcfa | |
parent | 7383118078a98112ca4036919e6654d8171d2274 (diff) | |
parent | ce34edb0eecec520d6d2cfec5bda57ca90a69f14 (diff) | |
download | riscv-isa-sim-6dcef28ed23f26d8f57880a3763f7a85da9fd08b.zip riscv-isa-sim-6dcef28ed23f26d8f57880a3763f7a85da9fd08b.tar.gz riscv-isa-sim-6dcef28ed23f26d8f57880a3763f7a85da9fd08b.tar.bz2 |
Merge pull request #1066 from plctlab/plct-nonfunc-fix
Fix some non-functional problems
59 files changed, 176 insertions, 170 deletions
diff --git a/riscv/cachesim.cc b/riscv/cachesim.cc index 48840cb..498d407 100644 --- a/riscv/cachesim.cc +++ b/riscv/cachesim.cc @@ -39,9 +39,9 @@ cache_sim_t* cache_sim_t::construct(const char* config, const char* name) void cache_sim_t::init() { - if(sets == 0 || (sets & (sets-1))) + if (sets == 0 || (sets & (sets-1))) help(); - if(linesz < 8 || (linesz & (linesz-1))) + if (linesz < 8 || (linesz & (linesz-1))) help(); idx_shift = 0; @@ -76,7 +76,7 @@ cache_sim_t::~cache_sim_t() void cache_sim_t::print_stats() { - if(read_accesses + write_accesses == 0) + if (read_accesses + write_accesses == 0) return; float mr = 100.0f*(read_misses+write_misses)/(read_accesses+write_accesses); diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index a3d35ea..d297f14 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -165,18 +165,18 @@ bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes) bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes) { D( - switch (len) { - case 4: - fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=0x%08x); " - "hartsel=0x%x\n", addr, (unsigned) len, *(uint32_t *) bytes, - dmcontrol.hartsel); - break; - default: - fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=...); " - "hartsel=0x%x\n", addr, (unsigned) len, dmcontrol.hartsel); - break; - } - ); + switch (len) { + case 4: + fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=0x%08x); " + "hartsel=0x%x\n", addr, (unsigned) len, *(uint32_t *) bytes, + dmcontrol.hartsel); + break; + default: + fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=...); " + "hartsel=0x%x\n", addr, (unsigned) len, dmcontrol.hartsel); + break; + } + ); uint8_t id_bytes[4]; uint32_t id = 0; @@ -215,11 +215,11 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes) } } if (dmcontrol.hartsel == id) { - if (0 == (debug_rom_flags[id] & (1 << DEBUG_ROM_FLAG_GO))){ - if (dmcontrol.hartsel == id) { - abstract_command_completed = true; - } + if (0 == (debug_rom_flags[id] & (1 << DEBUG_ROM_FLAG_GO))) { + if (dmcontrol.hartsel == id) { + abstract_command_completed = true; } + } } return true; } @@ -394,15 +394,15 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) result = set_field(result, DM_DMCONTROL_HASEL, dmcontrol.hasel); result = set_field(result, DM_DMCONTROL_HARTSELLO, dmcontrol.hartsel); result = set_field(result, DM_DMCONTROL_HARTRESET, dmcontrol.hartreset); - result = set_field(result, DM_DMCONTROL_NDMRESET, dmcontrol.ndmreset); + result = set_field(result, DM_DMCONTROL_NDMRESET, dmcontrol.ndmreset); result = set_field(result, DM_DMCONTROL_DMACTIVE, dmcontrol.dmactive); } break; case DM_DMSTATUS: { - dmstatus.allhalted = true; + dmstatus.allhalted = true; dmstatus.anyhalted = false; - dmstatus.allrunning = true; + dmstatus.allrunning = true; dmstatus.anyrunning = false; dmstatus.allnonexistant = true; dmstatus.allresumeack = true; @@ -430,8 +430,8 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) // non-existant hartsel. dmstatus.anynonexistant = (dmcontrol.hartsel >= nprocs); - dmstatus.allunavail = false; - dmstatus.anyunavail = false; + dmstatus.allunavail = false; + dmstatus.anyunavail = false; result = set_field(result, DM_DMSTATUS_IMPEBREAK, dmstatus.impebreak); @@ -439,15 +439,15 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) hart_state[dmcontrol.hartsel].havereset); result = set_field(result, DM_DMSTATUS_ANYHAVERESET, hart_state[dmcontrol.hartsel].havereset); - result = set_field(result, DM_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant); - result = set_field(result, DM_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail); - result = set_field(result, DM_DMSTATUS_ALLRUNNING, dmstatus.allrunning); - result = set_field(result, DM_DMSTATUS_ALLHALTED, dmstatus.allhalted); + result = set_field(result, DM_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant); + result = set_field(result, DM_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail); + result = set_field(result, DM_DMSTATUS_ALLRUNNING, dmstatus.allrunning); + result = set_field(result, DM_DMSTATUS_ALLHALTED, dmstatus.allhalted); result = set_field(result, DM_DMSTATUS_ALLRESUMEACK, dmstatus.allresumeack); - result = set_field(result, DM_DMSTATUS_ANYNONEXISTENT, dmstatus.anynonexistant); - result = set_field(result, DM_DMSTATUS_ANYUNAVAIL, dmstatus.anyunavail); - result = set_field(result, DM_DMSTATUS_ANYRUNNING, dmstatus.anyrunning); - result = set_field(result, DM_DMSTATUS_ANYHALTED, dmstatus.anyhalted); + result = set_field(result, DM_DMSTATUS_ANYNONEXISTENT, dmstatus.anynonexistant); + result = set_field(result, DM_DMSTATUS_ANYUNAVAIL, dmstatus.anyunavail); + result = set_field(result, DM_DMSTATUS_ANYRUNNING, dmstatus.anyrunning); + result = set_field(result, DM_DMSTATUS_ANYHALTED, dmstatus.anyhalted); result = set_field(result, DM_DMSTATUS_ANYRESUMEACK, dmstatus.anyresumeack); result = set_field(result, DM_DMSTATUS_AUTHENTICATED, dmstatus.authenticated); result = set_field(result, DM_DMSTATUS_AUTHBUSY, dmstatus.authbusy); diff --git a/riscv/debug_module.h b/riscv/debug_module.h index d79ce7d..8230557 100644 --- a/riscv/debug_module.h +++ b/riscv/debug_module.h @@ -11,16 +11,16 @@ class sim_t; class bus_t; typedef struct { - // Size of program_buffer in 32-bit words, as exposed to the rest of the - // world. - unsigned progbufsize; - unsigned max_sba_data_width; - bool require_authentication; - unsigned abstract_rti; - bool support_hasel; - bool support_abstract_csr_access; - bool support_haltgroups; - bool support_impebreak; + // Size of program_buffer in 32-bit words, as exposed to the rest of the + // world. + unsigned progbufsize; + unsigned max_sba_data_width; + bool require_authentication; + unsigned abstract_rti; + bool support_hasel; + bool support_abstract_csr_access; + bool support_haltgroups; + bool support_impebreak; } debug_module_config_t; typedef struct { @@ -54,12 +54,12 @@ typedef struct { } dmstatus_t; typedef enum cmderr { - CMDERR_NONE = 0, - CMDERR_BUSY = 1, - CMDERR_NOTSUP = 2, - CMDERR_EXCEPTION = 3, - CMDERR_HALTRESUME = 4, - CMDERR_OTHER = 7 + CMDERR_NONE = 0, + CMDERR_BUSY = 1, + CMDERR_NOTSUP = 2, + CMDERR_EXCEPTION = 3, + CMDERR_HALTRESUME = 4, + CMDERR_OTHER = 7 } cmderr_t; typedef struct { diff --git a/riscv/decode.h b/riscv/decode.h index 850863f..874d239 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -251,7 +251,7 @@ do { \ else { \ WRITE_FRD(value); \ } \ -} while(0) +} while (0) #define WRITE_FRD_F(value) \ do { \ if (p->extension_enabled(EXT_ZFINX)) \ @@ -259,7 +259,7 @@ do { \ else { \ WRITE_FRD(value); \ } \ -} while(0) +} while (0) #define WRITE_FRD_D(value) \ do { \ if (p->extension_enabled(EXT_ZFINX)) { \ @@ -272,7 +272,7 @@ do { \ } else { \ WRITE_FRD(value); \ } \ -} while(0) +} while (0) #define SHAMT (insn.i_imm() & 0x3F) #define BRANCH_TARGET (pc + insn.sb_imm()) diff --git a/riscv/entropy_source.h b/riscv/entropy_source.h index 184bec7..c2ee2c4 100644 --- a/riscv/entropy_source.h +++ b/riscv/entropy_source.h @@ -49,27 +49,27 @@ public: // the bare minimum. uint32_t return_status = OPST_ES16; - if(return_status == OPST_ES16) { + if (return_status == OPST_ES16) { - // Add some sampled entropy into the low 16 bits - uint16_t entropy = this -> get_two_random_bytes(); - result |= entropy; + // Add some sampled entropy into the low 16 bits + uint16_t entropy = this -> get_two_random_bytes(); + result |= entropy; - } else if(return_status == OPST_BIST) { + } else if (return_status == OPST_BIST) { - // Do nothing. + // Do nothing. - } else if(return_status == OPST_WAIT) { + } else if (return_status == OPST_WAIT) { - // Do nothing. + // Do nothing. - } else if(return_status == OPST_DEAD) { + } else if (return_status == OPST_DEAD) { - // Do nothing. Stay dead. + // Do nothing. Stay dead. } else { - // Unreachable. + // Unreachable. } @@ -92,25 +92,25 @@ public: // Read two random bytes from the entropy source file. uint16_t get_two_random_bytes() { - std::ifstream fh(this -> randomness_source, std::ios::binary); + std::ifstream fh(this -> randomness_source, std::ios::binary); - if(fh.is_open()) { + if (fh.is_open()) { - uint16_t random_bytes; + uint16_t random_bytes; - fh.read((char*)(&random_bytes), 2); + fh.read((char*)(&random_bytes), 2); - fh.close(); + fh.close(); - return random_bytes; + return random_bytes; - } else { + } else { - fprintf(stderr, "Could not open randomness source file:\n\t"); - fprintf(stderr, "%s", randomness_source.c_str()); - abort(); + fprintf(stderr, "Could not open randomness source file:\n\t"); + fprintf(stderr, "%s", randomness_source.c_str()); + abort(); - } + } } diff --git a/riscv/execute.cc b/riscv/execute.cc index 7cb16dd..1f9ddef 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -172,8 +172,10 @@ inline void processor_t::update_histogram(reg_t pc) // function calls. static inline reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch) { +#ifdef RISCV_ENABLE_COMMITLOG commit_log_reset(p); commit_log_stash_privilege(p); +#endif reg_t npc; try { @@ -238,18 +240,18 @@ void processor_t::step(size_t n) mmu_t* _mmu = mmu; #define advance_pc() \ - if (unlikely(invalid_pc(pc))) { \ - switch (pc) { \ - case PC_SERIALIZE_BEFORE: state.serialized = true; break; \ - case PC_SERIALIZE_AFTER: ++instret; break; \ - default: abort(); \ - } \ - pc = state.pc; \ - break; \ - } else { \ - state.pc = pc; \ - instret++; \ - } + if (unlikely(invalid_pc(pc))) { \ + switch (pc) { \ + case PC_SERIALIZE_BEFORE: state.serialized = true; break; \ + case PC_SERIALIZE_AFTER: ++instret; break; \ + default: abort(); \ + } \ + pc = state.pc; \ + break; \ + } else { \ + state.pc = pc; \ + instret++; \ + } try { diff --git a/riscv/insns/aes64ks1i.h b/riscv/insns/aes64ks1i.h index fff7109..3ce3c3f 100644 --- a/riscv/insns/aes64ks1i.h +++ b/riscv/insns/aes64ks1i.h @@ -10,7 +10,7 @@ uint8_t round_consts [10] = { uint8_t enc_rcon = insn.rcon() ; -if(enc_rcon > 0xA) { +if (enc_rcon > 0xA) { // Invalid opcode. throw trap_illegal_instruction(0); } @@ -19,7 +19,7 @@ uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF ; uint8_t rcon = 0 ; uint64_t result ; -if(enc_rcon != 0xA) { +if (enc_rcon != 0xA) { temp = (temp >> 8) | (temp << 24); // Rotate right by 8 rcon = round_consts[enc_rcon]; } diff --git a/riscv/insns/beq.h b/riscv/insns/beq.h index fd7e061..3d2c975 100644 --- a/riscv/insns/beq.h +++ b/riscv/insns/beq.h @@ -1,2 +1,2 @@ -if(RS1 == RS2) +if (RS1 == RS2) set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bge.h b/riscv/insns/bge.h index da0c68e..b2421c2 100644 --- a/riscv/insns/bge.h +++ b/riscv/insns/bge.h @@ -1,2 +1,2 @@ -if(sreg_t(RS1) >= sreg_t(RS2)) +if (sreg_t(RS1) >= sreg_t(RS2)) set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bgeu.h b/riscv/insns/bgeu.h index d764a34..f09b7f4 100644 --- a/riscv/insns/bgeu.h +++ b/riscv/insns/bgeu.h @@ -1,2 +1,2 @@ -if(RS1 >= RS2) +if (RS1 >= RS2) set_pc(BRANCH_TARGET); diff --git a/riscv/insns/blt.h b/riscv/insns/blt.h index c54fb76..cad064b 100644 --- a/riscv/insns/blt.h +++ b/riscv/insns/blt.h @@ -1,2 +1,2 @@ -if(sreg_t(RS1) < sreg_t(RS2)) +if (sreg_t(RS1) < sreg_t(RS2)) set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bltu.h b/riscv/insns/bltu.h index ff75e8a..b7c3300 100644 --- a/riscv/insns/bltu.h +++ b/riscv/insns/bltu.h @@ -1,2 +1,2 @@ -if(RS1 < RS2) +if (RS1 < RS2) set_pc(BRANCH_TARGET); diff --git a/riscv/insns/bne.h b/riscv/insns/bne.h index 1e6cb7c..e832fa1 100644 --- a/riscv/insns/bne.h +++ b/riscv/insns/bne.h @@ -1,2 +1,2 @@ -if(RS1 != RS2) +if (RS1 != RS2) set_pc(BRANCH_TARGET); diff --git a/riscv/insns/div.h b/riscv/insns/div.h index 9cbe8d6..fb62437 100644 --- a/riscv/insns/div.h +++ b/riscv/insns/div.h @@ -1,9 +1,9 @@ require_extension('M'); sreg_t lhs = sext_xlen(RS1); sreg_t rhs = sext_xlen(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(UINT64_MAX); -else if(lhs == INT64_MIN && rhs == -1) +else if (lhs == INT64_MIN && rhs == -1) WRITE_RD(lhs); else WRITE_RD(sext_xlen(lhs / rhs)); diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h index 31d7585..ed05818 100644 --- a/riscv/insns/divu.h +++ b/riscv/insns/divu.h @@ -1,7 +1,7 @@ require_extension('M'); reg_t lhs = zext_xlen(RS1); reg_t rhs = zext_xlen(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(UINT64_MAX); else WRITE_RD(sext_xlen(lhs / rhs)); diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h index e127619..bc7e9d2 100644 --- a/riscv/insns/divuw.h +++ b/riscv/insns/divuw.h @@ -2,7 +2,7 @@ require_extension('M'); require_rv64; reg_t lhs = zext32(RS1); reg_t rhs = zext32(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(UINT64_MAX); else WRITE_RD(sext32(lhs / rhs)); diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h index 11be17e..54409b0 100644 --- a/riscv/insns/divw.h +++ b/riscv/insns/divw.h @@ -2,7 +2,7 @@ require_extension('M'); require_rv64; sreg_t lhs = sext32(RS1); sreg_t rhs = sext32(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(UINT64_MAX); else WRITE_RD(sext32(lhs / rhs)); diff --git a/riscv/insns/kmmawb2.h b/riscv/insns/kmmawb2.h index 6b3aa0d..274f9dd 100644 --- a/riscv/insns/kmmawb2.h +++ b/riscv/insns/kmmawb2.h @@ -3,7 +3,7 @@ P_LOOP(32, { int64_t addop = 0; int64_t mres = 0; bool sat = false; - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1; addop = mres >> 16; } else { diff --git a/riscv/insns/kmmawb2_u.h b/riscv/insns/kmmawb2_u.h index f44346e..447a3f4 100644 --- a/riscv/insns/kmmawb2_u.h +++ b/riscv/insns/kmmawb2_u.h @@ -3,7 +3,7 @@ P_LOOP(32, { int64_t addop = 0; int64_t mres = 0; bool sat = false; - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1; addop = ((mres >> 15) + 1) >> 1; } else { diff --git a/riscv/insns/kmmawt2.h b/riscv/insns/kmmawt2.h index 3cd72de..6eb22ac 100644 --- a/riscv/insns/kmmawt2.h +++ b/riscv/insns/kmmawt2.h @@ -3,7 +3,7 @@ P_LOOP(32, { int64_t addop = 0; int64_t mres = 0; bool sat = false; - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { mres = ((int64_t) ps1 * P_SH(ps2, 1)) << 1; addop = mres >> 16; } else { diff --git a/riscv/insns/kmmawt2_u.h b/riscv/insns/kmmawt2_u.h index 7fe378c..b82e090 100644 --- a/riscv/insns/kmmawt2_u.h +++ b/riscv/insns/kmmawt2_u.h @@ -3,7 +3,7 @@ P_LOOP(32, { int64_t addop = 0; int64_t mres = 0; bool sat = false; - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { mres = ((int64_t) ps1 * P_SH(ps2, 1)) << 1; addop = ((mres >> 15) + 1) >> 1; } else { diff --git a/riscv/insns/kmmwb2.h b/riscv/insns/kmmwb2.h index 272f738..d08b0ef 100644 --- a/riscv/insns/kmmwb2.h +++ b/riscv/insns/kmmwb2.h @@ -1,6 +1,6 @@ require_vector_vs; P_LOOP(32, { - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { int64_t mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1; pd = mres >> 16; } else { diff --git a/riscv/insns/kmmwb2_u.h b/riscv/insns/kmmwb2_u.h index b5a5006..d308bf3 100644 --- a/riscv/insns/kmmwb2_u.h +++ b/riscv/insns/kmmwb2_u.h @@ -1,6 +1,6 @@ require_vector_vs; P_LOOP(32, { - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) { int64_t mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1; pd = ((mres >> 15) + 1) >> 1; } else { diff --git a/riscv/insns/kmmwt2.h b/riscv/insns/kmmwt2.h index 73d3dc8..38ba9b1 100644 --- a/riscv/insns/kmmwt2.h +++ b/riscv/insns/kmmwt2.h @@ -1,6 +1,6 @@ require_vector_vs; P_LOOP(32, { - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { int64_t mres = ((int64_t) ps1 * P_SH(ps2, 1)) << 1; pd = mres >> 16; } else { diff --git a/riscv/insns/kmmwt2_u.h b/riscv/insns/kmmwt2_u.h index 1f525a8..e855786 100644 --- a/riscv/insns/kmmwt2_u.h +++ b/riscv/insns/kmmwt2_u.h @@ -1,6 +1,6 @@ require_vector_vs; P_LOOP(32, { - if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { + if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) { int64_t mres = ((int64_t) ps1 * P_SH(ps2, 1)) << 1; pd = ((mres >> 15) + 1) >> 1; } else { diff --git a/riscv/insns/kslra16_u.h b/riscv/insns/kslra16_u.h index 8335f3e..27bb77c 100644 --- a/riscv/insns/kslra16_u.h +++ b/riscv/insns/kslra16_u.h @@ -3,7 +3,7 @@ P_X_LOOP(16, 5, { if (ssa < 0) { sa = -ssa; sa = (sa == 16) ? 15 : sa; - if(sa != 0) + if (sa != 0) pd = ((ps1 >> (sa - 1)) + 1) >> 1; else pd = ps1; diff --git a/riscv/insns/kslra32_u.h b/riscv/insns/kslra32_u.h index d53c8fe..b9c06cf 100644 --- a/riscv/insns/kslra32_u.h +++ b/riscv/insns/kslra32_u.h @@ -4,7 +4,7 @@ P_X_LOOP(32, 6, { if (ssa < 0) { sa = -ssa; sa = (sa == 32) ? 31 : sa; - if(sa != 0) + if (sa != 0) pd = ((ps1 >> (sa - 1)) + 1) >> 1; else pd = ps1; diff --git a/riscv/insns/kslra8_u.h b/riscv/insns/kslra8_u.h index 620f3bd..340283f 100644 --- a/riscv/insns/kslra8_u.h +++ b/riscv/insns/kslra8_u.h @@ -3,7 +3,7 @@ P_X_LOOP(8, 4, { if (ssa < 0) { sa = -ssa; sa = (sa == 8) ? 7 : sa; - if(sa != 0) + if (sa != 0) pd = ((ps1 >> (sa - 1)) + 1) >> 1; else pd = ps1; diff --git a/riscv/insns/kwmmul.h b/riscv/insns/kwmmul.h index b0ab8d4..ca654f2 100644 --- a/riscv/insns/kwmmul.h +++ b/riscv/insns/kwmmul.h @@ -1,6 +1,6 @@ require_vector_vs; P_LOOP(32, { - if((INT32_MIN != ps1) | (INT32_MIN != ps2)) { + if ((INT32_MIN != ps1) | (INT32_MIN != ps2)) { int64_t mres = ((int64_t) ps1 * (int64_t) ps2) << 1; pd = mres >> 32; } else { diff --git a/riscv/insns/kwmmul_u.h b/riscv/insns/kwmmul_u.h index c2045e1..b435561 100644 --- a/riscv/insns/kwmmul_u.h +++ b/riscv/insns/kwmmul_u.h @@ -1,6 +1,6 @@ require_vector_vs; P_LOOP(32, { - if((INT32_MIN != ps1) | (INT32_MIN != ps2)) { + if ((INT32_MIN != ps1) | (INT32_MIN != ps2)) { int64_t mres = ((int64_t) ps1 * (int64_t) ps2) << 1; pd = ((mres >> 31) + 1) >> 1; } else { diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h index 8587995..d2ee066 100644 --- a/riscv/insns/rem.h +++ b/riscv/insns/rem.h @@ -1,9 +1,9 @@ require_extension('M'); sreg_t lhs = sext_xlen(RS1); sreg_t rhs = sext_xlen(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(lhs); -else if(lhs == INT64_MIN && rhs == -1) +else if (lhs == INT64_MIN && rhs == -1) WRITE_RD(0); else WRITE_RD(sext_xlen(lhs % rhs)); diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h index e74774c..676747a 100644 --- a/riscv/insns/remu.h +++ b/riscv/insns/remu.h @@ -1,7 +1,7 @@ require_extension('M'); reg_t lhs = zext_xlen(RS1); reg_t rhs = zext_xlen(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(sext_xlen(RS1)); else WRITE_RD(sext_xlen(lhs % rhs)); diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h index b239c8f..caa1583 100644 --- a/riscv/insns/remuw.h +++ b/riscv/insns/remuw.h @@ -2,7 +2,7 @@ require_extension('M'); require_rv64; reg_t lhs = zext32(RS1); reg_t rhs = zext32(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(sext32(lhs)); else WRITE_RD(sext32(lhs % rhs)); diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h index 56221cc..076096c 100644 --- a/riscv/insns/remw.h +++ b/riscv/insns/remw.h @@ -2,7 +2,7 @@ require_extension('M'); require_rv64; sreg_t lhs = sext32(RS1); sreg_t rhs = sext32(RS2); -if(rhs == 0) +if (rhs == 0) WRITE_RD(lhs); else WRITE_RD(sext32(lhs % rhs)); diff --git a/riscv/insns/rsub64.h b/riscv/insns/rsub64.h index 397c973..2a58485 100644 --- a/riscv/insns/rsub64.h +++ b/riscv/insns/rsub64.h @@ -2,7 +2,7 @@ P_64_PROFILE({ rd = (rs1 - rs2) >> 1; if (rs1 > 0 && rs2 < 0) { rd &= ~((reg_t)1 << 63); - } else if(rs1 < 0 && rs2 > 0) { + } else if (rs1 < 0 && rs2 > 0) { rd |= ((reg_t)1 << 63); } }) diff --git a/riscv/insns/sra16_u.h b/riscv/insns/sra16_u.h index c28178e..6fcc398 100644 --- a/riscv/insns/sra16_u.h +++ b/riscv/insns/sra16_u.h @@ -1,5 +1,5 @@ P_X_LOOP(16, 4, { - if(sa > 0) + if (sa > 0) pd = ((ps1 >> (sa - 1)) + 1) >> 1; else pd = ps1; diff --git a/riscv/insns/sra32_u.h b/riscv/insns/sra32_u.h index e062a88..1a4488c 100644 --- a/riscv/insns/sra32_u.h +++ b/riscv/insns/sra32_u.h @@ -1,6 +1,6 @@ require_rv64; P_X_LOOP(32, 5, { - if(sa > 0) + if (sa > 0) pd = (((uint64_t)(ps1 >> (sa - 1))) + 1) >> 1; else pd = ps1; diff --git a/riscv/insns/sra8_u.h b/riscv/insns/sra8_u.h index 7061fc4..1f47623 100644 --- a/riscv/insns/sra8_u.h +++ b/riscv/insns/sra8_u.h @@ -1,5 +1,5 @@ P_X_LOOP(8, 3, { - if(sa > 0) + if (sa > 0) pd = ((ps1 >> (sa - 1)) + 1) >> 1; else pd = ps1; diff --git a/riscv/insns/vdiv_vx.h b/riscv/insns/vdiv_vx.h index 4052952..2b93eac 100644 --- a/riscv/insns/vdiv_vx.h +++ b/riscv/insns/vdiv_vx.h @@ -1,9 +1,9 @@ // vdiv.vx vd, vs2, rs1 VI_VX_LOOP ({ - if(rs1 == 0) + if (rs1 == 0) vd = -1; - else if(vs2 == (INT64_MIN >> (64 - sew)) && rs1 == -1) + else if (vs2 == (INT64_MIN >> (64 - sew)) && rs1 == -1) vd = vs2; else vd = vs2 / rs1; diff --git a/riscv/insns/vdivu_vv.h b/riscv/insns/vdivu_vv.h index ef6e777..89aeed6 100644 --- a/riscv/insns/vdivu_vv.h +++ b/riscv/insns/vdivu_vv.h @@ -1,7 +1,7 @@ // vdivu.vv vd, vs2, vs1 VI_VV_ULOOP ({ - if(vs1 == 0) + if (vs1 == 0) vd = -1; else vd = vs2 / vs1; diff --git a/riscv/insns/vdivu_vx.h b/riscv/insns/vdivu_vx.h index 7ffe1c6..ce3e964 100644 --- a/riscv/insns/vdivu_vx.h +++ b/riscv/insns/vdivu_vx.h @@ -1,7 +1,7 @@ // vdivu.vx vd, vs2, rs1 VI_VX_ULOOP ({ - if(rs1 == 0) + if (rs1 == 0) vd = -1; else vd = vs2 / rs1; diff --git a/riscv/insns/vfmv_f_s.h b/riscv/insns/vfmv_f_s.h index 81605ea..0f3cf8c 100644 --- a/riscv/insns/vfmv_f_s.h +++ b/riscv/insns/vfmv_f_s.h @@ -9,7 +9,7 @@ require(STATE.frm->read() < 0x5); reg_t rs2_num = insn.rs2(); uint64_t vs2_0 = 0; const reg_t sew = P.VU.vsew; -switch(sew) { +switch (sew) { case e16: vs2_0 = P.VU.elt<uint16_t>(rs2_num, 0); break; diff --git a/riscv/insns/vfmv_s_f.h b/riscv/insns/vfmv_s_f.h index edc376e..e50ad41 100644 --- a/riscv/insns/vfmv_s_f.h +++ b/riscv/insns/vfmv_s_f.h @@ -11,7 +11,7 @@ reg_t vl = P.VU.vl->read(); if (vl > 0 && P.VU.vstart->read() < vl) { reg_t rd_num = insn.rd(); - switch(P.VU.vsew) { + switch (P.VU.vsew) { case e16: P.VU.elt<uint16_t>(rd_num, 0, true) = f16(FRS1).v; break; diff --git a/riscv/insns/vmsbf_m.h b/riscv/insns/vmsbf_m.h index 6147f6d..1275872 100644 --- a/riscv/insns/vmsbf_m.h +++ b/riscv/insns/vmsbf_m.h @@ -24,7 +24,7 @@ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { uint64_t res = 0; if (!has_one && !vs2_lsb) { res = 1; - } else if(!has_one && vs2_lsb) { + } else if (!has_one && vs2_lsb) { has_one = true; } vd = (vd & ~mmask) | ((res << mpos) & mmask); diff --git a/riscv/insns/vmsif_m.h b/riscv/insns/vmsif_m.h index 447813f..cbcbc2a 100644 --- a/riscv/insns/vmsif_m.h +++ b/riscv/insns/vmsif_m.h @@ -23,7 +23,7 @@ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) { uint64_t res = 0; if (!has_one && !vs2_lsb) { res = 1; - } else if(!has_one && vs2_lsb) { + } else if (!has_one && vs2_lsb) { has_one = true; res = 1; } diff --git a/riscv/insns/vmsof_m.h b/riscv/insns/vmsof_m.h index b9edcf3..9bd4f0c 100644 --- a/riscv/insns/vmsof_m.h +++ b/riscv/insns/vmsof_m.h @@ -21,7 +21,7 @@ for (reg_t i = P.VU.vstart->read() ; i < vl; ++i) { if (insn.v_vm() == 1 || (insn.v_vm() == 0 && do_mask)) { uint64_t &vd = P.VU.elt<uint64_t>(rd_num, midx, true); uint64_t res = 0; - if(!has_one && vs2_lsb) { + if (!has_one && vs2_lsb) { has_one = true; res = 1; } diff --git a/riscv/insns/vmv_s_x.h b/riscv/insns/vmv_s_x.h index b66855b..23a6b56 100644 --- a/riscv/insns/vmv_s_x.h +++ b/riscv/insns/vmv_s_x.h @@ -8,7 +8,7 @@ if (vl > 0 && P.VU.vstart->read() < vl) { reg_t rd_num = insn.rd(); reg_t sew = P.VU.vsew; - switch(sew) { + switch (sew) { case e8: P.VU.elt<uint8_t>(rd_num, 0, true) = RS1; break; diff --git a/riscv/insns/vmv_x_s.h b/riscv/insns/vmv_x_s.h index d33c3e5..8451d6a 100644 --- a/riscv/insns/vmv_x_s.h +++ b/riscv/insns/vmv_x_s.h @@ -6,7 +6,7 @@ reg_t rs1 = RS1; reg_t sew = P.VU.vsew; reg_t rs2_num = insn.rs2(); -switch(sew) { +switch (sew) { case e8: WRITE_RD(P.VU.elt<int8_t>(rs2_num, 0)); break; diff --git a/riscv/insns/vrem_vv.h b/riscv/insns/vrem_vv.h index 260716a..5c58fa4 100644 --- a/riscv/insns/vrem_vv.h +++ b/riscv/insns/vrem_vv.h @@ -3,7 +3,7 @@ VI_VV_LOOP ({ if (vs1 == 0) vd = vs2; - else if(vs2 == -(((intmax_t)1) << (sew - 1)) && vs1 == -1) + else if (vs2 == -(((intmax_t)1) << (sew - 1)) && vs1 == -1) vd = 0; else { vd = vs2 % vs1; diff --git a/riscv/insns/vsadd_vi.h b/riscv/insns/vsadd_vi.h index 7e3b652..3a8b1d4 100644 --- a/riscv/insns/vsadd_vi.h +++ b/riscv/insns/vsadd_vi.h @@ -2,7 +2,7 @@ VI_CHECK_SSS(false); VI_LOOP_BASE bool sat = false; -switch(sew) { +switch (sew) { case e8: { VI_PARAMS(e8); vd = sat_add<int8_t, uint8_t>(vs2, vsext(simm5, sew), sat); diff --git a/riscv/insns/vsadd_vv.h b/riscv/insns/vsadd_vv.h index 60ad5f3..d4cfe78 100644 --- a/riscv/insns/vsadd_vv.h +++ b/riscv/insns/vsadd_vv.h @@ -2,7 +2,7 @@ VI_CHECK_SSS(true); VI_LOOP_BASE bool sat = false; -switch(sew) { +switch (sew) { case e8: { VV_PARAMS(e8); vd = sat_add<int8_t, uint8_t>(vs2, vs1, sat); diff --git a/riscv/insns/vsadd_vx.h b/riscv/insns/vsadd_vx.h index bf68f15..e5e6c40 100644 --- a/riscv/insns/vsadd_vx.h +++ b/riscv/insns/vsadd_vx.h @@ -2,7 +2,7 @@ VI_CHECK_SSS(false); VI_LOOP_BASE bool sat = false; -switch(sew) { +switch (sew) { case e8: { VX_PARAMS(e8); vd = sat_add<int8_t, uint8_t>(vs2, rs1, sat); diff --git a/riscv/insns/vslide1up_vx.h b/riscv/insns/vslide1up_vx.h index 33cb9ed..256419e 100644 --- a/riscv/insns/vslide1up_vx.h +++ b/riscv/insns/vslide1up_vx.h @@ -6,24 +6,24 @@ if (i != 0) { if (sew == e8) { VI_XI_SLIDEUP_PARAMS(e8, 1); vd = vs2; - } else if(sew == e16) { + } else if (sew == e16) { VI_XI_SLIDEUP_PARAMS(e16, 1); vd = vs2; - } else if(sew == e32) { + } else if (sew == e32) { VI_XI_SLIDEUP_PARAMS(e32, 1); vd = vs2; - } else if(sew == e64) { + } else if (sew == e64) { VI_XI_SLIDEUP_PARAMS(e64, 1); vd = vs2; } } else { if (sew == e8) { P.VU.elt<uint8_t>(rd_num, 0, true) = RS1; - } else if(sew == e16) { + } else if (sew == e16) { P.VU.elt<uint16_t>(rd_num, 0, true) = RS1; - } else if(sew == e32) { + } else if (sew == e32) { P.VU.elt<uint32_t>(rd_num, 0, true) = RS1; - } else if(sew == e64) { + } else if (sew == e64) { P.VU.elt<uint64_t>(rd_num, 0, true) = RS1; } } diff --git a/riscv/interactive.cc b/riscv/interactive.cc index 4b29069..c6a9f80 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -150,17 +150,17 @@ void sim_t::interactive() // first get commands from file, if cmd_file has been set if (cmd_file && !feof(cmd_file) && fscanf(cmd_file,"%" STR(MAX_CMD_STR) "[^\n]\n", cmd_str)==1) { // up to MAX_CMD_STR characters before \n, skipping \n - s = cmd_str; - // while we get input from file, output goes to stderr - sout_.rdbuf(std::cerr.rdbuf()); + s = cmd_str; + // while we get input from file, output goes to stderr + sout_.rdbuf(std::cerr.rdbuf()); } else { - // when there are no commands left from file or if there was no file from the beginning - cmd_file = NULL; // mark file pointer as being not valid, so any method can test this easily + // when there are no commands left from file or if there was no file from the beginning + cmd_file = NULL; // mark file pointer as being not valid, so any method can test this easily #ifdef HAVE_BOOST_ASIO - s = rin(&bout); // get command string from socket or terminal + s = rin(&bout); // get command string from socket or terminal #else - std::cerr << ": " << std::flush; - s = readline(2); // 2 is stderr, but when doing reads it reverts to stdin + std::cerr << ": " << std::flush; + s = readline(2); // 2 is stderr, but when doing reads it reverts to stdin #endif } @@ -211,15 +211,17 @@ void sim_t::interactive_help(const std::string& cmd, const std::vector<std::stri "fregd <core> <reg> # Display double precision <reg> in <core>\n" "vreg <core> [reg] # Display vector [reg] (all if omitted) in <core>\n" "pc <core> # Show current PC in <core>\n" - "mem <hex addr> # Show contents of physical memory\n" - "str <core> <hex addr> # Show NUL-terminated C string at <hex addr> in core <core>\n" + "mem [core] <hex addr> # Show contents of virtual memory <hex addr> in [core] (physical memory <hex addr> if omitted)\n" + "str [core] <hex addr> # Show NUL-terminated C string at virtual address <hex addr> in [core] (physical address <hex addr> if omitted)\n" "until reg <core> <reg> <val> # Stop when <reg> in <core> hits <val>\n" + "untiln reg <core> <reg> <val> # Run noisy and stop when <reg> in <core> hits <val>\n" "until pc <core> <val> # Stop when PC in <core> hits <val>\n" "untiln pc <core> <val> # Run noisy and stop when PC in <core> hits <val>\n" - "until mem <addr> <val> # Stop when memory <addr> becomes <val>\n" + "until mem [core] <addr> <val> # Stop when virtual memory <addr> in [core] (physical address <addr> if omitted) becomes <val>\n" + "untiln mem [core] <addr> <val> # Run noisy and stop when virtual memory <addr> in [core] (physical address <addr> if omitted) becomes <val>\n" "while reg <core> <reg> <val> # Run while <reg> in <core> is <val>\n" "while pc <core> <val> # Run while PC in <core> is <val>\n" - "while mem <addr> <val> # Run while memory <addr> is <val>\n" + "while mem [core] <addr> <val> # Run while virtual memory <addr> in [core] (physical memory <addr> if omitted) is <val>\n" "run [count] # Resume noisy execution (until CTRL+C, or [count] insns)\n" "r [count] Alias for run\n" "rs [count] # Resume silent execution (until CTRL+C, or [count] insns)\n" @@ -269,7 +271,7 @@ reg_t sim_t::get_pc(const std::vector<std::string>& args) void sim_t::interactive_pc(const std::string& cmd, const std::vector<std::string>& args) { - if(args.size() != 1) + if (args.size() != 1) throw trap_interactive(); processor_t *p = get_core(args[0]); @@ -307,7 +309,7 @@ reg_t sim_t::get_reg(const std::vector<std::string>& args) freg_t sim_t::get_freg(const std::vector<std::string>& args, int size) { - if(args.size() != 2) + if (args.size() != 2) throw trap_interactive(); processor_t *p = get_core(args[0]); @@ -361,9 +363,9 @@ void sim_t::interactive_vreg(const std::string& cmd, const std::vector<std::stri for (int r = rstart; r < rend; ++r) { out << std::setfill (' ') << std::left << std::setw(4) << vr_name[r] << std::right << ": "; - for (int e = num_elem-1; e >= 0; --e){ + for (int e = num_elem-1; e >= 0; --e) { uint64_t val; - switch(elen){ + switch (elen) { case 8: val = p->VU.elt<uint64_t>(r, e); out << std::dec << "[" << e << "]: 0x" << std::hex << std::setfill ('0') << std::setw(16) << val << " "; @@ -389,7 +391,7 @@ void sim_t::interactive_vreg(const std::string& cmd, const std::vector<std::stri void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::string>& args) { if (args.size() < 1) - throw trap_interactive(); + throw trap_interactive(); processor_t *p = get_core(args[0]); int max_xlen = p->get_isa().get_max_xlen(); @@ -402,14 +404,14 @@ void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::strin for (int r = 0; r < NXPR; ++r) { out << std::setfill(' ') << std::setw(4) << xpr_name[r] - << ": 0x" << std::setfill('0') << std::setw(max_xlen/4) - << zext(p->get_state()->XPR[r], max_xlen); + << ": 0x" << std::setfill('0') << std::setw(max_xlen/4) + << zext(p->get_state()->XPR[r], max_xlen); if ((r + 1) % 4 == 0) out << std::endl; } } else { - out << "0x" << std::setfill('0') << std::setw(max_xlen/4) - << zext(get_reg(args), max_xlen) << std::endl; + out << "0x" << std::setfill('0') << std::setw(max_xlen/4) + << zext(get_reg(args), max_xlen) << std::endl; } } @@ -473,7 +475,7 @@ reg_t sim_t::get_mem(const std::vector<std::string>& args) if (addr == LONG_MAX) addr = strtoul(addr_str.c_str(),NULL,16); - switch(addr % 8) + switch (addr % 8) { case 0: val = mmu->load_uint64(addr); @@ -520,7 +522,7 @@ void sim_t::interactive_str(const std::string& cmd, const std::vector<std::strin std::ostream out(sout_.rdbuf()); char ch; - while((ch = mmu->load_uint8(addr++))) + while ((ch = mmu->load_uint8(addr++))) out << ch; out << std::endl; diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h index c57436e..2aed262 100644 --- a/riscv/isa_parser.h +++ b/riscv/isa_parser.h @@ -69,7 +69,7 @@ typedef enum { class isa_parser_t { public: isa_parser_t(const char* str, const char *priv); - ~isa_parser_t(){}; + ~isa_parser_t() {}; unsigned get_max_xlen() const { return max_xlen; } reg_t get_max_isa() const { return max_isa; } std::string get_isa_string() const { return isa_string; } diff --git a/riscv/processor.cc b/riscv/processor.cc index 0325c51..620a6f4 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -512,7 +512,6 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT { int new_vlmul = 0; if (vtype->read() != newType) { - vtype->write_raw(newType); vsew = 1 << (extract64(newType, 3, 3) + 3); new_vlmul = int8_t(extract64(newType, 0, 3) << 5) >> 5; vflmul = new_vlmul >= 0 ? 1 << new_vlmul : 1.0 / (1 << -new_vlmul); @@ -527,6 +526,8 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT if (vill) { vlmax = 0; vtype->write_raw(UINT64_MAX << (p->get_xlen() - 1)); + } else { + vtype->write_raw(newType); } } @@ -588,7 +589,7 @@ void processor_t::reset() put_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT); } - for (auto e : custom_extensions) // reset any extensions + for (auto e : custom_extensions) // reset any extensions e.second->reset(); if (sim) diff --git a/riscv/processor.h b/riscv/processor.h index 88ddf70..073b25b 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -406,7 +406,7 @@ public: // vector element for varies SEW template<class T> - T& elt(reg_t vReg, reg_t n, bool is_write = false){ + T& elt(reg_t vReg, reg_t n, bool is_write = false) { assert(vsew != 0); assert((VLEN >> 3)/sizeof(T) > 0); reg_t elts_per_reg = (VLEN >> 3) / (sizeof(T)); @@ -453,7 +453,7 @@ public: vstart_alu(false) { } - ~vectorUnit_t(){ + ~vectorUnit_t() { free(reg_file); reg_file = 0; } diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index 9ff383c..19207f7 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -56,7 +56,7 @@ static inline bool is_overlapped_widen(const int astart, int asize, if (astart < bstart && is_overlapped(astart, asize, bstart, bsize) && !is_overlapped(astart, asize, bstart + bsize, bsize)) { - return false; + return false; } else { return std::max(aend, bend) - std::min(astart, bstart) < asize + bsize; } diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 3629e35..70b4313 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -50,6 +50,7 @@ static void help(int exit_code = 1) fprintf(stderr, " This flag can be used multiple times.\n"); fprintf(stderr, " The extlib flag for the library must come first.\n"); fprintf(stderr, " --log-cache-miss Generate a log of cache miss\n"); + fprintf(stderr, " --log-commits Generate a log of commits info\n"); fprintf(stderr, " --extension=<name> Specify RoCC Extension\n"); fprintf(stderr, " This flag can be used multiple times.\n"); fprintf(stderr, " --extlib=<name> Shared library to load\n"); |