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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-12 23:21:34 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-17 10:00:52 +0800 |
| commit | c0b3fdcbaba99576393c57607985a0009bb2ebb1 (patch) | |
| tree | 0576152cb3360fca861e4db4903d126238e734a1 | |
| parent | d6f332d63aa5141cacd652cc5476e9d01ceb91e8 (diff) | |
| download | riscv-isa-sim-c0b3fdcbaba99576393c57607985a0009bb2ebb1.zip riscv-isa-sim-c0b3fdcbaba99576393c57607985a0009bb2ebb1.tar.gz riscv-isa-sim-c0b3fdcbaba99576393c57607985a0009bb2ebb1.tar.bz2 | |
modify the check for "state->prv >= PRV_M" to "state->prv == PRV_M"
prv can never be larger than PRV_M
| -rw-r--r-- | riscv/csrs.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 57778c3..c43812b 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -885,7 +885,7 @@ satp_csr_t::satp_csr_t(processor_t* const proc, const reg_t addr): void satp_csr_t::verify_permissions(insn_t insn, bool write) const { base_atp_csr_t::verify_permissions(insn, write); if (get_field(state->mstatus->read(), MSTATUS_TVM)) - require(state->prv >= PRV_M); + require(state->prv == PRV_M); } virtualized_satp_csr_t::virtualized_satp_csr_t(processor_t* const proc, satp_csr_t_p orig, csr_t_p virt): |