Merge pull request #831 from plctlab/plct-upstream-zfinx

add support for zfinx v1.0

94 files changed, 289 insertions, 215 deletions

diff --git a/README.md b/README.md
index afc7187..1935b04 100644
--- a/README.md
+++ b/README.md
@@ -28,6 +28,7 @@ Spike supports the following RISC-V ISA features:
   - Zbc extension, v1.0
   - Zbs extension, v1.0
   - Zfh and Zfhmin half-precision floating-point extensions, v1.0
+  - Zfinx extension, v1.0
   - Zmmul integer multiplication extension, v1.0
   - Zicbom, Zicbop, Zicboz cache-block maintenance extensions, v1.0
   - Conformance to both RVWMO and RVTSO (Spike is sequentially consistent)
diff --git a/riscv/csrs.cc b/riscv/csrs.cc
index 3f487b4..7de49a7 100644
--- a/riscv/csrs.cc
+++ b/riscv/csrs.cc
@@ -394,8 +394,8 @@ base_status_csr_t::base_status_csr_t(processor_t* const proc, const reg_t addr):
 reg_t base_status_csr_t::compute_sstatus_write_mask() const noexcept {
   // If a configuration has FS bits, they will always be accessible no
   // matter the state of misa.
-  const bool has_fs = proc->extension_enabled('S') || proc->extension_enabled('F')
-              || proc->extension_enabled('V');
+  const bool has_fs = (proc->extension_enabled('S') || proc->extension_enabled('F')
+              || proc->extension_enabled('V')) && !proc->extension_enabled(EXT_ZFINX);
   const bool has_vs = proc->extension_enabled('V');
   return 0
     | (proc->extension_enabled('S') ? (SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP) : 0)
@@ -1201,8 +1201,8 @@ float_csr_t::float_csr_t(processor_t* const proc, const reg_t addr, const reg_t
 
 void float_csr_t::verify_permissions(insn_t insn, bool write) const {
   masked_csr_t::verify_permissions(insn, write);
-  require_fp;
-  if (!proc->extension_enabled('F'))
+  require_fs;
+  if (!proc->extension_enabled('F') && !proc->extension_enabled(EXT_ZFINX))
     throw trap_illegal_instruction(insn.bits());
 
   if (proc->extension_enabled(EXT_SMSTATEEN) && proc->extension_enabled(EXT_ZFINX)) {
diff --git a/riscv/decode.h b/riscv/decode.h
index 72b4a6b..850863f 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -223,14 +223,56 @@ private:
 #define RVC_SP READ_REG(X_SP)
 
 // FPU macros
+#define READ_ZDINX_REG(reg) (xlen == 32 ? f64(READ_REG_PAIR(reg)) : f64(STATE.XPR[reg] & (uint64_t)-1))
+#define READ_FREG_H(reg) (p->extension_enabled(EXT_ZFINX) ? f16(STATE.XPR[reg] & (uint16_t)-1) : f16(READ_FREG(reg)))
+#define READ_FREG_F(reg) (p->extension_enabled(EXT_ZFINX) ? f32(STATE.XPR[reg] & (uint32_t)-1) : f32(READ_FREG(reg)))
+#define READ_FREG_D(reg) (p->extension_enabled(EXT_ZFINX) ? READ_ZDINX_REG(reg) : f64(READ_FREG(reg)))
 #define FRS1 READ_FREG(insn.rs1())
 #define FRS2 READ_FREG(insn.rs2())
 #define FRS3 READ_FREG(insn.rs3())
+#define FRS1_H READ_FREG_H(insn.rs1())
+#define FRS1_F READ_FREG_F(insn.rs1())
+#define FRS1_D READ_FREG_D(insn.rs1())
+#define FRS2_H READ_FREG_H(insn.rs2())
+#define FRS2_F READ_FREG_F(insn.rs2())
+#define FRS2_D READ_FREG_D(insn.rs2())
+#define FRS3_H READ_FREG_H(insn.rs3())
+#define FRS3_F READ_FREG_F(insn.rs3())
+#define FRS3_D READ_FREG_D(insn.rs3())
 #define dirty_fp_state  STATE.sstatus->dirty(SSTATUS_FS)
 #define dirty_ext_state STATE.sstatus->dirty(SSTATUS_XS)
 #define dirty_vs_state  STATE.sstatus->dirty(SSTATUS_VS)
 #define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state)
 #define WRITE_FRD(value) WRITE_FREG(insn.rd(), value)
+#define WRITE_FRD_H(value) \
+do { \
+  if (p->extension_enabled(EXT_ZFINX)) \
+    WRITE_REG(insn.rd(), sext_xlen((int16_t)((value).v))); \
+  else { \
+    WRITE_FRD(value); \
+  } \
+} while(0)
+#define WRITE_FRD_F(value) \
+do { \
+  if (p->extension_enabled(EXT_ZFINX)) \
+    WRITE_REG(insn.rd(), sext_xlen((value).v)); \
+  else { \
+    WRITE_FRD(value); \
+  } \
+} while(0)
+#define WRITE_FRD_D(value) \
+do { \
+  if (p->extension_enabled(EXT_ZFINX)) { \
+    if (xlen == 32) { \
+      uint64_t val = (value).v; \
+      WRITE_RD_PAIR(val); \
+    } else { \
+      WRITE_REG(insn.rd(), (value).v); \
+    } \
+  } else { \
+    WRITE_FRD(value); \
+  } \
+} while(0)
  
 #define SHAMT (insn.i_imm() & 0x3F)
 #define BRANCH_TARGET (pc + insn.sb_imm())
@@ -250,7 +292,8 @@ private:
 #define require_extension(s) require(p->extension_enabled(s))
 #define require_either_extension(A,B) require(p->extension_enabled(A) || p->extension_enabled(B));
 #define require_impl(s) require(p->supports_impl(s))
-#define require_fp          require(STATE.sstatus->enabled(SSTATUS_FS))
+#define require_fs          require(STATE.sstatus->enabled(SSTATUS_FS))
+#define require_fp          STATE.fflags->verify_permissions(insn, false)
 #define require_accelerator require(STATE.sstatus->enabled(SSTATUS_XS))
 #define require_vector_vs   require(STATE.sstatus->enabled(SSTATUS_VS))
 #define require_vector(alu) \
diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h
index 4a436e2..9bfff5f 100644
--- a/riscv/insns/fadd_d.h
+++ b/riscv/insns/fadd_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_add(f64(FRS1), f64(FRS2)));
+WRITE_FRD_D(f64_add(FRS1_D, FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fadd_h.h b/riscv/insns/fadd_h.h
index 2b646ae..f57e5fa 100644
--- a/riscv/insns/fadd_h.h
+++ b/riscv/insns/fadd_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_add(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_add(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h
index cc18d58..7a40b1b 100644
--- a/riscv/insns/fadd_s.h
+++ b/riscv/insns/fadd_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_add(f32(FRS1), f32(FRS2)));
+WRITE_FRD_F(f32_add(FRS1_F, FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fclass_d.h b/riscv/insns/fclass_d.h
index 9456123..a355062 100644
--- a/riscv/insns/fclass_d.h
+++ b/riscv/insns/fclass_d.h
@@ -1,3 +1,3 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_RD(f64_classify(f64(FRS1)));
+WRITE_RD(f64_classify(FRS1_D));
diff --git a/riscv/insns/fclass_h.h b/riscv/insns/fclass_h.h
index 066a2d2..2638ac8 100644
--- a/riscv/insns/fclass_h.h
+++ b/riscv/insns/fclass_h.h
@@ -1,3 +1,3 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_RD(f16_classify(f16(FRS1)));
+WRITE_RD(f16_classify(FRS1_H));
diff --git a/riscv/insns/fclass_s.h b/riscv/insns/fclass_s.h
index a392db8..3d529ad 100644
--- a/riscv/insns/fclass_s.h
+++ b/riscv/insns/fclass_s.h
@@ -1,3 +1,3 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_RD(f32_classify(f32(FRS1)));
+WRITE_RD(f32_classify(FRS1_F));
diff --git a/riscv/insns/fcvt_d_h.h b/riscv/insns/fcvt_d_h.h
index 04e9ff4..061a271 100644
--- a/riscv/insns/fcvt_d_h.h
+++ b/riscv/insns/fcvt_d_h.h
@@ -1,6 +1,6 @@
-require_extension(EXT_ZFHMIN);
-require_extension('D');
+require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN);
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_to_f64(f16(FRS1)));
+WRITE_FRD_D(f16_to_f64(FRS1_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_l.h b/riscv/insns/fcvt_d_l.h
index 08716cf..7788f1f 100644
--- a/riscv/insns/fcvt_d_l.h
+++ b/riscv/insns/fcvt_d_l.h
@@ -1,6 +1,6 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i64_to_f64(RS1));
+WRITE_FRD_D(i64_to_f64(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_lu.h b/riscv/insns/fcvt_d_lu.h
index 306d7fe..edb694f 100644
--- a/riscv/insns/fcvt_d_lu.h
+++ b/riscv/insns/fcvt_d_lu.h
@@ -1,6 +1,6 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui64_to_f64(RS1));
+WRITE_FRD_D(ui64_to_f64(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_s.h b/riscv/insns/fcvt_d_s.h
index 5f805b0..8039e94 100644
--- a/riscv/insns/fcvt_d_s.h
+++ b/riscv/insns/fcvt_d_s.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_to_f64(f32(FRS1)));
+WRITE_FRD_D(f32_to_f64(FRS1_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h
index 4c4861c..e3375fa 100644
--- a/riscv/insns/fcvt_d_w.h
+++ b/riscv/insns/fcvt_d_w.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f64((int32_t)RS1));
+WRITE_FRD_D(i32_to_f64((int32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_wu.h b/riscv/insns/fcvt_d_wu.h
index 1dbf218..d903561 100644
--- a/riscv/insns/fcvt_d_wu.h
+++ b/riscv/insns/fcvt_d_wu.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f64((uint32_t)RS1));
+WRITE_FRD_D(ui32_to_f64((uint32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_d.h b/riscv/insns/fcvt_h_d.h
index e9987b7..e06b1a5 100644
--- a/riscv/insns/fcvt_h_d.h
+++ b/riscv/insns/fcvt_h_d.h
@@ -1,6 +1,6 @@
-require_extension(EXT_ZFHMIN);
-require_extension('D');
+require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN);
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_to_f16(f64(FRS1)));
+WRITE_FRD_H(f64_to_f16(FRS1_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_l.h b/riscv/insns/fcvt_h_l.h
index 39178c2..31e8a1e 100644
--- a/riscv/insns/fcvt_h_l.h
+++ b/riscv/insns/fcvt_h_l.h
@@ -1,6 +1,6 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i64_to_f16(RS1));
+WRITE_FRD_H(i64_to_f16(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_lu.h b/riscv/insns/fcvt_h_lu.h
index a872c48..189b160 100644
--- a/riscv/insns/fcvt_h_lu.h
+++ b/riscv/insns/fcvt_h_lu.h
@@ -1,6 +1,6 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui64_to_f16(RS1));
+WRITE_FRD_H(ui64_to_f16(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_s.h b/riscv/insns/fcvt_h_s.h
index ce39d81..57ba005 100644
--- a/riscv/insns/fcvt_h_s.h
+++ b/riscv/insns/fcvt_h_s.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFHMIN);
+require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_to_f16(f32(FRS1)));
+WRITE_FRD_H(f32_to_f16(FRS1_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_w.h b/riscv/insns/fcvt_h_w.h
index c082454..de4cbe5 100644
--- a/riscv/insns/fcvt_h_w.h
+++ b/riscv/insns/fcvt_h_w.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f16((int32_t)RS1));
+WRITE_FRD_H(i32_to_f16((int32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_h_wu.h b/riscv/insns/fcvt_h_wu.h
index 9f2f5f6..230c354 100644
--- a/riscv/insns/fcvt_h_wu.h
+++ b/riscv/insns/fcvt_h_wu.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f16((uint32_t)RS1));
+WRITE_FRD_H(ui32_to_f16((uint32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_l_d.h b/riscv/insns/fcvt_l_d.h
index c09e6c4..f2374d2 100644
--- a/riscv/insns/fcvt_l_d.h
+++ b/riscv/insns/fcvt_l_d.h
@@ -1,6 +1,6 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f64_to_i64(f64(FRS1), RM, true));
+WRITE_RD(f64_to_i64(FRS1_D, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_l_h.h b/riscv/insns/fcvt_l_h.h
index 5a1fea8..3b63027 100644
--- a/riscv/insns/fcvt_l_h.h
+++ b/riscv/insns/fcvt_l_h.h
@@ -1,6 +1,6 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f16_to_i64(f16(FRS1), RM, true));
+WRITE_RD(f16_to_i64(FRS1_H, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_l_s.h b/riscv/insns/fcvt_l_s.h
index 267e0eb..d121a65 100644
--- a/riscv/insns/fcvt_l_s.h
+++ b/riscv/insns/fcvt_l_s.h
@@ -1,6 +1,6 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f32_to_i64(f32(FRS1), RM, true));
+WRITE_RD(f32_to_i64(FRS1_F, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_lu_d.h b/riscv/insns/fcvt_lu_d.h
index 3a02120..939bc0e 100644
--- a/riscv/insns/fcvt_lu_d.h
+++ b/riscv/insns/fcvt_lu_d.h
@@ -1,6 +1,6 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f64_to_ui64(f64(FRS1), RM, true));
+WRITE_RD(f64_to_ui64(FRS1_D, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_lu_h.h b/riscv/insns/fcvt_lu_h.h
index f1454c3..d27f175 100644
--- a/riscv/insns/fcvt_lu_h.h
+++ b/riscv/insns/fcvt_lu_h.h
@@ -1,6 +1,6 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f16_to_ui64(f16(FRS1), RM, true));
+WRITE_RD(f16_to_ui64(FRS1_H, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_lu_s.h b/riscv/insns/fcvt_lu_s.h
index 94115a3..69c95ef 100644
--- a/riscv/insns/fcvt_lu_s.h
+++ b/riscv/insns/fcvt_lu_s.h
@@ -1,6 +1,6 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(f32_to_ui64(f32(FRS1), RM, true));
+WRITE_RD(f32_to_ui64(FRS1_F, RM, true));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_d.h b/riscv/insns/fcvt_s_d.h
index 4033335..f3cd26e 100644
--- a/riscv/insns/fcvt_s_d.h
+++ b/riscv/insns/fcvt_s_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_to_f32(f64(FRS1)));
+WRITE_FRD_F(f64_to_f32(FRS1_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_h.h b/riscv/insns/fcvt_s_h.h
index 22cdd72..346440a 100644
--- a/riscv/insns/fcvt_s_h.h
+++ b/riscv/insns/fcvt_s_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFHMIN);
+require_either_extension(EXT_ZFHMIN, EXT_ZHINXMIN);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_to_f32(f16(FRS1)));
+WRITE_FRD_F(f16_to_f32(FRS1_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_l.h b/riscv/insns/fcvt_s_l.h
index 9abcc80..1d096d2 100644
--- a/riscv/insns/fcvt_s_l.h
+++ b/riscv/insns/fcvt_s_l.h
@@ -1,6 +1,6 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i64_to_f32(RS1));
+WRITE_FRD_F(i64_to_f32(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_lu.h b/riscv/insns/fcvt_s_lu.h
index 70c676e..e4e84cf 100644
--- a/riscv/insns/fcvt_s_lu.h
+++ b/riscv/insns/fcvt_s_lu.h
@@ -1,6 +1,6 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui64_to_f32(RS1));
+WRITE_FRD_F(ui64_to_f32(RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h
index 1ddabd8..75c87db 100644
--- a/riscv/insns/fcvt_s_w.h
+++ b/riscv/insns/fcvt_s_w.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(i32_to_f32((int32_t)RS1));
+WRITE_FRD_F(i32_to_f32((int32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_wu.h b/riscv/insns/fcvt_s_wu.h
index c1394c3..ec90fad 100644
--- a/riscv/insns/fcvt_s_wu.h
+++ b/riscv/insns/fcvt_s_wu.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(ui32_to_f32((uint32_t)RS1));
+WRITE_FRD_F(ui32_to_f32((uint32_t)RS1));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_w_d.h b/riscv/insns/fcvt_w_d.h
index 28eb245..a839f4b 100644
--- a/riscv/insns/fcvt_w_d.h
+++ b/riscv/insns/fcvt_w_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f64_to_i32(f64(FRS1), RM, true)));
+WRITE_RD(sext32(f64_to_i32(FRS1_D, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_w_h.h b/riscv/insns/fcvt_w_h.h
index fe8bb48..97e49a5 100644
--- a/riscv/insns/fcvt_w_h.h
+++ b/riscv/insns/fcvt_w_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f16_to_i32(f16(FRS1), RM, true)));
+WRITE_RD(sext32(f16_to_i32(FRS1_H, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_w_s.h b/riscv/insns/fcvt_w_s.h
index d30f1b4..6aeb510 100644
--- a/riscv/insns/fcvt_w_s.h
+++ b/riscv/insns/fcvt_w_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f32_to_i32(f32(FRS1), RM, true)));
+WRITE_RD(sext32(f32_to_i32(FRS1_F, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_wu_d.h b/riscv/insns/fcvt_wu_d.h
index 5cdc004..906f003 100644
--- a/riscv/insns/fcvt_wu_d.h
+++ b/riscv/insns/fcvt_wu_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f64_to_ui32(f64(FRS1), RM, true)));
+WRITE_RD(sext32(f64_to_ui32(FRS1_D, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_wu_h.h b/riscv/insns/fcvt_wu_h.h
index bf6648d..ce11143 100644
--- a/riscv/insns/fcvt_wu_h.h
+++ b/riscv/insns/fcvt_wu_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f16_to_ui32(f16(FRS1), RM, true)));
+WRITE_RD(sext32(f16_to_ui32(FRS1_H, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fcvt_wu_s.h b/riscv/insns/fcvt_wu_s.h
index 034d681..a8b8455 100644
--- a/riscv/insns/fcvt_wu_s.h
+++ b/riscv/insns/fcvt_wu_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_RD(sext32(f32_to_ui32(f32(FRS1), RM, true)));
+WRITE_RD(sext32(f32_to_ui32(FRS1_F, RM, true)));
 set_fp_exceptions;
diff --git a/riscv/insns/fdiv_d.h b/riscv/insns/fdiv_d.h
index ae7911a..990afca 100644
--- a/riscv/insns/fdiv_d.h
+++ b/riscv/insns/fdiv_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_div(f64(FRS1), f64(FRS2)));
+WRITE_FRD_D(f64_div(FRS1_D, FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fdiv_h.h b/riscv/insns/fdiv_h.h
index a169eae..91c518b 100644
--- a/riscv/insns/fdiv_h.h
+++ b/riscv/insns/fdiv_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_div(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_div(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fdiv_s.h b/riscv/insns/fdiv_s.h
index c74ff04..180b41d 100644
--- a/riscv/insns/fdiv_s.h
+++ b/riscv/insns/fdiv_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_div(f32(FRS1), f32(FRS2)));
+WRITE_FRD_F(f32_div(FRS1_F, FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/feq_d.h b/riscv/insns/feq_d.h
index 541ed5b..9585bad 100644
--- a/riscv/insns/feq_d.h
+++ b/riscv/insns/feq_d.h
@@ -1,4 +1,4 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_RD(f64_eq(f64(FRS1), f64(FRS2)));
+WRITE_RD(f64_eq(FRS1_D, FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/feq_h.h b/riscv/insns/feq_h.h
index 47e75a5..5988db9 100644
--- a/riscv/insns/feq_h.h
+++ b/riscv/insns/feq_h.h
@@ -1,4 +1,4 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_RD(f16_eq(f16(FRS1), f16(FRS2)));
+WRITE_RD(f16_eq(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/feq_s.h b/riscv/insns/feq_s.h
index 489bea6..97b57c2 100644
--- a/riscv/insns/feq_s.h
+++ b/riscv/insns/feq_s.h
@@ -1,4 +1,4 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_RD(f32_eq(f32(FRS1), f32(FRS2)));
+WRITE_RD(f32_eq(FRS1_F, FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fle_d.h b/riscv/insns/fle_d.h
index 419a36f..17b4932 100644
--- a/riscv/insns/fle_d.h
+++ b/riscv/insns/fle_d.h
@@ -1,4 +1,4 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_RD(f64_le(f64(FRS1), f64(FRS2)));
+WRITE_RD(f64_le(FRS1_D, FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fle_h.h b/riscv/insns/fle_h.h
index 9fc5968..31ed8a7 100644
--- a/riscv/insns/fle_h.h
+++ b/riscv/insns/fle_h.h
@@ -1,4 +1,4 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_RD(f16_le(f16(FRS1), f16(FRS2)));
+WRITE_RD(f16_le(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fle_s.h b/riscv/insns/fle_s.h
index 5c0124e..e26f055 100644
--- a/riscv/insns/fle_s.h
+++ b/riscv/insns/fle_s.h
@@ -1,4 +1,4 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_RD(f32_le(f32(FRS1), f32(FRS2)));
+WRITE_RD(f32_le(FRS1_F, FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/flt_d.h b/riscv/insns/flt_d.h
index 7176a96..5fb0572 100644
--- a/riscv/insns/flt_d.h
+++ b/riscv/insns/flt_d.h
@@ -1,4 +1,4 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_RD(f64_lt(f64(FRS1), f64(FRS2)));
+WRITE_RD(f64_lt(FRS1_D, FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/flt_h.h b/riscv/insns/flt_h.h
index f516a38..dd6bc79 100644
--- a/riscv/insns/flt_h.h
+++ b/riscv/insns/flt_h.h
@@ -1,4 +1,4 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_RD(f16_lt(f16(FRS1), f16(FRS2)));
+WRITE_RD(f16_lt(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/flt_s.h b/riscv/insns/flt_s.h
index 40acc34..2f50ed6 100644
--- a/riscv/insns/flt_s.h
+++ b/riscv/insns/flt_s.h
@@ -1,4 +1,4 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_RD(f32_lt(f32(FRS1), f32(FRS2)));
+WRITE_RD(f32_lt(FRS1_F, FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fmadd_d.h b/riscv/insns/fmadd_d.h
index ab22beb..07a8b25 100644
--- a/riscv/insns/fmadd_d.h
+++ b/riscv/insns/fmadd_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3)));
+WRITE_FRD_D(f64_mulAdd(FRS1_D, FRS2_D, FRS3_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fmadd_h.h b/riscv/insns/fmadd_h.h
index 6551de5..5428897 100644
--- a/riscv/insns/fmadd_h.h
+++ b/riscv/insns/fmadd_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_mulAdd(f16(FRS1), f16(FRS2), f16(FRS3)));
+WRITE_FRD_H(f16_mulAdd(FRS1_H, FRS2_H, FRS3_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fmadd_s.h b/riscv/insns/fmadd_s.h
index e919190..5a72cf8 100644
--- a/riscv/insns/fmadd_s.h
+++ b/riscv/insns/fmadd_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3)));
+WRITE_FRD_F(f32_mulAdd(FRS1_F, FRS2_F, FRS3_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h
index 11491f5..3e05b7e 100644
--- a/riscv/insns/fmax_d.h
+++ b/riscv/insns/fmax_d.h
@@ -1,9 +1,9 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-bool greater = f64_lt_quiet(f64(FRS2), f64(FRS1)) ||
-               (f64_eq(f64(FRS2), f64(FRS1)) && (f64(FRS2).v & F64_SIGN));
-if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v))
-  WRITE_FRD(f64(defaultNaNF64UI));
+bool greater = f64_lt_quiet(FRS2_D, FRS1_D) ||
+              (f64_eq(FRS2_D, FRS1_D) && (FRS2_D.v & F64_SIGN));
+if (isNaNF64UI(FRS1_D.v) && isNaNF64UI(FRS2_D.v))
+  WRITE_FRD_D(f64(defaultNaNF64UI));
 else
-  WRITE_FRD(greater || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
+  WRITE_FRD_D((greater || isNaNF64UI(FRS2_D.v) ? FRS1_D : FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fmax_h.h b/riscv/insns/fmax_h.h
index 3d4c40e..c864258 100644
--- a/riscv/insns/fmax_h.h
+++ b/riscv/insns/fmax_h.h
@@ -1,4 +1,4 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_FRD(f16_max(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_max(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h
index 41d8f92..17d8b3c 100644
--- a/riscv/insns/fmax_s.h
+++ b/riscv/insns/fmax_s.h
@@ -1,9 +1,9 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-bool greater = f32_lt_quiet(f32(FRS2), f32(FRS1)) ||
-               (f32_eq(f32(FRS2), f32(FRS1)) && (f32(FRS2).v & F32_SIGN));
-if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v))
-  WRITE_FRD(f32(defaultNaNF32UI));
+bool greater = f32_lt_quiet(FRS2_F, FRS1_F) ||
+               (f32_eq(FRS2_F, FRS1_F) && (FRS2_F.v & F32_SIGN));
+if (isNaNF32UI(FRS1_F.v) && isNaNF32UI(FRS2_F.v))
+  WRITE_FRD_F(f32(defaultNaNF32UI));
 else
-  WRITE_FRD(greater || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+  WRITE_FRD_F((greater || isNaNF32UI(FRS2_F.v) ? FRS1_F : FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h
index 5cf349d..f60a73e 100644
--- a/riscv/insns/fmin_d.h
+++ b/riscv/insns/fmin_d.h
@@ -1,9 +1,9 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-bool less = f64_lt_quiet(f64(FRS1), f64(FRS2)) ||
-            (f64_eq(f64(FRS1), f64(FRS2)) && (f64(FRS1).v & F64_SIGN));
-if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v))
-  WRITE_FRD(f64(defaultNaNF64UI));
+bool less = f64_lt_quiet(FRS1_D, FRS2_D) ||
+            (f64_eq(FRS1_D, FRS2_D) && (FRS1_D.v & F64_SIGN));
+if (isNaNF64UI(FRS1_D.v) && isNaNF64UI(FRS2_D.v))
+  WRITE_FRD_D(f64(defaultNaNF64UI));
 else
-  WRITE_FRD(less || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
+  WRITE_FRD_D((less || isNaNF64UI(FRS2_D.v) ? FRS1_D : FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_h.h b/riscv/insns/fmin_h.h
index 5fb1404..cd02f20 100644
--- a/riscv/insns/fmin_h.h
+++ b/riscv/insns/fmin_h.h
@@ -1,4 +1,4 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_FRD(f16_min(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_min(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h
index 19e1193..476a586 100644
--- a/riscv/insns/fmin_s.h
+++ b/riscv/insns/fmin_s.h
@@ -1,9 +1,9 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-bool less = f32_lt_quiet(f32(FRS1), f32(FRS2)) ||
-            (f32_eq(f32(FRS1), f32(FRS2)) && (f32(FRS1).v & F32_SIGN));
-if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v))
-  WRITE_FRD(f32(defaultNaNF32UI));
+bool less = f32_lt_quiet(FRS1_F, FRS2_F) ||
+            (f32_eq(FRS1_F, FRS2_F) && (FRS1_F.v & F32_SIGN));
+if (isNaNF32UI(FRS1_F.v) && isNaNF32UI(FRS2_F.v))
+  WRITE_FRD_F(f32(defaultNaNF32UI));
 else
-  WRITE_FRD(less || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+  WRITE_FRD_F((less || isNaNF32UI(FRS2_F.v) ? FRS1_F : FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fmsub_d.h b/riscv/insns/fmsub_d.h
index 5b5bc0f..1a7d784 100644
--- a/riscv/insns/fmsub_d.h
+++ b/riscv/insns/fmsub_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN)));
+WRITE_FRD_D(f64_mulAdd(FRS1_D, FRS2_D, f64(FRS3_D.v ^ F64_SIGN)));
 set_fp_exceptions;
diff --git a/riscv/insns/fmsub_h.h b/riscv/insns/fmsub_h.h
index 934291f..dc6a8e6 100644
--- a/riscv/insns/fmsub_h.h
+++ b/riscv/insns/fmsub_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_mulAdd(f16(FRS1), f16(FRS2), f16(f16(FRS3).v ^ F16_SIGN)));
+WRITE_FRD_H(f16_mulAdd(FRS1_H, FRS2_H, f16(FRS3_H.v ^ F16_SIGN)));
 set_fp_exceptions;
diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h
index d46c887..179cc2f 100644
--- a/riscv/insns/fmsub_s.h
+++ b/riscv/insns/fmsub_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
+WRITE_FRD_F(f32_mulAdd(FRS1_F, FRS2_F, f32(FRS3_F.v ^ F32_SIGN)));
 set_fp_exceptions;
diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h
index 9189d8d..e5caa34 100644
--- a/riscv/insns/fmul_d.h
+++ b/riscv/insns/fmul_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mul(f64(FRS1), f64(FRS2)));
+WRITE_FRD_D(f64_mul(FRS1_D, FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fmul_h.h b/riscv/insns/fmul_h.h
index 0152df8..dc7f9c4 100644
--- a/riscv/insns/fmul_h.h
+++ b/riscv/insns/fmul_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_mul(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_mul(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h
index 145d5ce..9cf30b4 100644
--- a/riscv/insns/fmul_s.h
+++ b/riscv/insns/fmul_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mul(f32(FRS1), f32(FRS2)));
+WRITE_FRD_F(f32_mul(FRS1_F, FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h
index e8dd743..a2a14e9 100644
--- a/riscv/insns/fnmadd_d.h
+++ b/riscv/insns/fnmadd_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN)));
+WRITE_FRD_D(f64_mulAdd(f64(FRS1_D.v ^ F64_SIGN), FRS2_D, f64(FRS3_D.v ^ F64_SIGN)));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmadd_h.h b/riscv/insns/fnmadd_h.h
index e4c619e..b1ca283 100644
--- a/riscv/insns/fnmadd_h.h
+++ b/riscv/insns/fnmadd_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_mulAdd(f16(f16(FRS1).v ^ F16_SIGN), f16(FRS2), f16(f16(FRS3).v ^ F16_SIGN)));
+WRITE_FRD_H(f16_mulAdd(f16(FRS1_H.v ^ F16_SIGN), FRS2_H, f16(FRS3_H.v ^ F16_SIGN)));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h
index 1c2996e..683257a 100644
--- a/riscv/insns/fnmadd_s.h
+++ b/riscv/insns/fnmadd_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
+WRITE_FRD_F(f32_mulAdd(f32(FRS1_F.v ^ F32_SIGN), FRS2_F, f32(FRS3_F.v ^ F32_SIGN)));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h
index c29a0b9..9352c3f 100644
--- a/riscv/insns/fnmsub_d.h
+++ b/riscv/insns/fnmsub_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(FRS3)));
+WRITE_FRD_D(f64_mulAdd(f64(FRS1_D.v ^ F64_SIGN), FRS2_D, FRS3_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmsub_h.h b/riscv/insns/fnmsub_h.h
index 0410c3b..e05fcd1 100644
--- a/riscv/insns/fnmsub_h.h
+++ b/riscv/insns/fnmsub_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_mulAdd(f16(f16(FRS1).v ^ F16_SIGN), f16(FRS2), f16(FRS3)));
+WRITE_FRD_H(f16_mulAdd(f16(FRS1_H.v ^ F16_SIGN), FRS2_H, FRS3_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h
index 4c61fc7..b22b3db 100644
--- a/riscv/insns/fnmsub_s.h
+++ b/riscv/insns/fnmsub_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(FRS3)));
+WRITE_FRD_F(f32_mulAdd(f32(FRS1_F.v ^ F32_SIGN), FRS2_F, FRS3_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fsgnj_d.h b/riscv/insns/fsgnj_d.h
index 78f9ce7..8f02fd1 100644
--- a/riscv/insns/fsgnj_d.h
+++ b/riscv/insns/fsgnj_d.h
@@ -1,3 +1,3 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_FRD(fsgnj64(FRS1, FRS2, false, false));
+WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), false, false));
diff --git a/riscv/insns/fsgnj_h.h b/riscv/insns/fsgnj_h.h
index 79d50f5..080f27d 100644
--- a/riscv/insns/fsgnj_h.h
+++ b/riscv/insns/fsgnj_h.h
@@ -1,3 +1,3 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_FRD(fsgnj16(FRS1, FRS2, false, false));
+WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), false, false));
diff --git a/riscv/insns/fsgnj_s.h b/riscv/insns/fsgnj_s.h
index c1a70cb..ea511b8 100644
--- a/riscv/insns/fsgnj_s.h
+++ b/riscv/insns/fsgnj_s.h
@@ -1,3 +1,3 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_FRD(fsgnj32(FRS1, FRS2, false, false));
+WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), false, false));
diff --git a/riscv/insns/fsgnjn_d.h b/riscv/insns/fsgnjn_d.h
index f02c311..870a979 100644
--- a/riscv/insns/fsgnjn_d.h
+++ b/riscv/insns/fsgnjn_d.h
@@ -1,3 +1,3 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_FRD(fsgnj64(FRS1, FRS2, true, false));
+WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), true, false));
diff --git a/riscv/insns/fsgnjn_h.h b/riscv/insns/fsgnjn_h.h
index ebb4ac9..1d7bf03 100644
--- a/riscv/insns/fsgnjn_h.h
+++ b/riscv/insns/fsgnjn_h.h
@@ -1,3 +1,3 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_FRD(fsgnj16(FRS1, FRS2, true, false));
+WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), true, false));
\ No newline at end of file
diff --git a/riscv/insns/fsgnjn_q.h b/riscv/insns/fsgnjn_q.h
index 38c7bbf..dcf7235 100644
--- a/riscv/insns/fsgnjn_q.h
+++ b/riscv/insns/fsgnjn_q.h
@@ -1,3 +1,3 @@
 require_extension('Q');
 require_fp;
-WRITE_FRD(fsgnj128(FRS1, FRS2, true, false));
+WRITE_FRD(fsgnj128(FRS1, FRS2, true, false));
\ No newline at end of file
diff --git a/riscv/insns/fsgnjn_s.h b/riscv/insns/fsgnjn_s.h
index 35906d6..a0994b4 100644
--- a/riscv/insns/fsgnjn_s.h
+++ b/riscv/insns/fsgnjn_s.h
@@ -1,3 +1,3 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_FRD(fsgnj32(FRS1, FRS2, true, false));
+WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), true, false));
diff --git a/riscv/insns/fsgnjx_d.h b/riscv/insns/fsgnjx_d.h
index c121737..25906f0 100644
--- a/riscv/insns/fsgnjx_d.h
+++ b/riscv/insns/fsgnjx_d.h
@@ -1,3 +1,3 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
-WRITE_FRD(fsgnj64(FRS1, FRS2, false, true));
+WRITE_FRD_D(fsgnj64(freg(FRS1_D), freg(FRS2_D), false, true));
diff --git a/riscv/insns/fsgnjx_h.h b/riscv/insns/fsgnjx_h.h
index 9310269..1d29bb1 100644
--- a/riscv/insns/fsgnjx_h.h
+++ b/riscv/insns/fsgnjx_h.h
@@ -1,3 +1,3 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
-WRITE_FRD(fsgnj16(FRS1, FRS2, false, true));
+WRITE_FRD_H(fsgnj16(freg(FRS1_H), freg(FRS2_H), false, true));
diff --git a/riscv/insns/fsgnjx_s.h b/riscv/insns/fsgnjx_s.h
index 4d5c624..9bc0798 100644
--- a/riscv/insns/fsgnjx_s.h
+++ b/riscv/insns/fsgnjx_s.h
@@ -1,3 +1,3 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
-WRITE_FRD(fsgnj32(FRS1, FRS2, false, true));
+WRITE_FRD_F(fsgnj32(freg(FRS1_F), freg(FRS2_F), false, true));
diff --git a/riscv/insns/fsqrt_d.h b/riscv/insns/fsqrt_d.h
index da138ba..363b457 100644
--- a/riscv/insns/fsqrt_d.h
+++ b/riscv/insns/fsqrt_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_sqrt(f64(FRS1)));
+WRITE_FRD_D(f64_sqrt(FRS1_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fsqrt_h.h b/riscv/insns/fsqrt_h.h
index 138d572..fea429b 100644
--- a/riscv/insns/fsqrt_h.h
+++ b/riscv/insns/fsqrt_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_sqrt(f16(FRS1)));
+WRITE_FRD_H(f16_sqrt(FRS1_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fsqrt_s.h b/riscv/insns/fsqrt_s.h
index 7476846..d44503a 100644
--- a/riscv/insns/fsqrt_s.h
+++ b/riscv/insns/fsqrt_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_sqrt(f32(FRS1)));
+WRITE_FRD_F(f32_sqrt(FRS1_F));
 set_fp_exceptions;
diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h
index 1418a06..4f8bf50 100644
--- a/riscv/insns/fsub_d.h
+++ b/riscv/insns/fsub_d.h
@@ -1,5 +1,5 @@
-require_extension('D');
+require_either_extension('D', EXT_ZDINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f64_sub(f64(FRS1), f64(FRS2)));
+WRITE_FRD_D(f64_sub(FRS1_D, FRS2_D));
 set_fp_exceptions;
diff --git a/riscv/insns/fsub_h.h b/riscv/insns/fsub_h.h
index 43b51cc..f7006fb 100644
--- a/riscv/insns/fsub_h.h
+++ b/riscv/insns/fsub_h.h
@@ -1,5 +1,5 @@
-require_extension(EXT_ZFH);
+require_either_extension(EXT_ZFH, EXT_ZHINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f16_sub(f16(FRS1), f16(FRS2)));
+WRITE_FRD_H(f16_sub(FRS1_H, FRS2_H));
 set_fp_exceptions;
diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h
index f6183ea..1a33ffd 100644
--- a/riscv/insns/fsub_s.h
+++ b/riscv/insns/fsub_s.h
@@ -1,5 +1,5 @@
-require_extension('F');
+require_either_extension('F', EXT_ZFINX);
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_sub(f32(FRS1), f32(FRS2)));
+WRITE_FRD_F(f32_sub(FRS1_F, FRS2_F));
 set_fp_exceptions;
diff --git a/riscv/insns/vfslide1down_vf.h b/riscv/insns/vfslide1down_vf.h
index 66eeacc..40f3c18 100644
--- a/riscv/insns/vfslide1down_vf.h
+++ b/riscv/insns/vfslide1down_vf.h
@@ -23,13 +23,13 @@ if (i != vl - 1) {
 } else {
   switch (P.VU.vsew) {
     case e16:
-      P.VU.elt<float16_t>(rd_num, vl - 1, true) = f16(FRS1);
+      P.VU.elt<float16_t>(rd_num, vl - 1, true) = FRS1_H;
       break;
     case e32:
-      P.VU.elt<float32_t>(rd_num, vl - 1, true) = f32(FRS1);
+      P.VU.elt<float32_t>(rd_num, vl - 1, true) = FRS1_F;
       break;
     case e64:
-      P.VU.elt<float64_t>(rd_num, vl - 1, true) = f64(FRS1);
+      P.VU.elt<float64_t>(rd_num, vl - 1, true) = FRS1_D;
       break;
   }
 }
diff --git a/riscv/insns/vfslide1up_vf.h b/riscv/insns/vfslide1up_vf.h
index b9c2817..4e4e499 100644
--- a/riscv/insns/vfslide1up_vf.h
+++ b/riscv/insns/vfslide1up_vf.h
@@ -23,13 +23,13 @@ if (i != 0) {
 } else {
   switch (P.VU.vsew) {
     case e16:
-      P.VU.elt<float16_t>(rd_num, 0, true) = f16(FRS1);
+      P.VU.elt<float16_t>(rd_num, 0, true) = FRS1_H;
       break;
     case e32:
-      P.VU.elt<float32_t>(rd_num, 0, true) = f32(FRS1);
+      P.VU.elt<float32_t>(rd_num, 0, true) = FRS1_F;
       break;
     case e64:
-      P.VU.elt<float64_t>(rd_num, 0, true) = f64(FRS1);
+      P.VU.elt<float64_t>(rd_num, 0, true) = FRS1_D;
       break;
   }
 }
diff --git a/riscv/interactive.cc b/riscv/interactive.cc
index f41be2c..4b29069 100644
--- a/riscv/interactive.cc
+++ b/riscv/interactive.cc
@@ -305,19 +305,33 @@ reg_t sim_t::get_reg(const std::vector<std::string>& args)
   return p->get_state()->XPR[r];
 }
 
-freg_t sim_t::get_freg(const std::vector<std::string>& args)
+freg_t sim_t::get_freg(const std::vector<std::string>& args, int size)
 {
   if(args.size() != 2)
     throw trap_interactive();
 
   processor_t *p = get_core(args[0]);
-  int r = std::find(fpr_name, fpr_name + NFPR, args[1]) - fpr_name;
-  if (r == NFPR)
-    r = atoi(args[1].c_str());
-  if (r >= NFPR)
-    throw trap_interactive();
-
-  return p->get_state()->FPR[r];
+  if (p->extension_enabled(EXT_ZFINX)) {
+    int r = std::find(xpr_name, xpr_name + NXPR, args[1]) - xpr_name;
+    if (r == NXPR)
+      r = atoi(args[1].c_str());
+    if (r >= NXPR)
+      throw trap_interactive();
+    if ((p->get_xlen() == 32) && (size == 64)) {
+      if (r % 2 != 0)
+        throw trap_interactive();
+      return freg(f64(r== 0 ? reg_t(0) : (READ_REG(r + 1) << 32) + zext32(READ_REG(r))));
+    } else { //xlen >= size
+      return {p->get_state()->XPR[r] | ~(((uint64_t)-1) >> (64 - size)) ,(uint64_t)-1};
+    }
+  } else {
+    int r = std::find(fpr_name, fpr_name + NFPR, args[1]) - fpr_name;
+    if (r == NFPR)
+      r = atoi(args[1].c_str());
+    if (r >= NFPR)
+      throw trap_interactive();
+    return p->get_state()->FPR[r];
+  }
 }
 
 void sim_t::interactive_vreg(const std::string& cmd, const std::vector<std::string>& args)
@@ -408,7 +422,7 @@ union fpr
 
 void sim_t::interactive_freg(const std::string& cmd, const std::vector<std::string>& args)
 {
-  freg_t r = get_freg(args);
+  freg_t r = get_freg(args, 64);
 
   std::ostream out(sout_.rdbuf());
   out << std::hex << "0x" << std::setfill ('0') << std::setw(16) << r.v[1] << std::setw(16) << r.v[0] << std::endl;
@@ -417,7 +431,7 @@ void sim_t::interactive_freg(const std::string& cmd, const std::vector<std::stri
 void sim_t::interactive_fregh(const std::string& cmd, const std::vector<std::string>& args)
 {
   fpr f;
-  f.r = freg(f16_to_f32(f16(get_freg(args))));
+  f.r = freg(f16_to_f32(f16(get_freg(args, 16))));
 
   std::ostream out(sout_.rdbuf());
   out << (isBoxedF32(f.r) ? (double)f.s : NAN) << std::endl;
@@ -426,7 +440,7 @@ void sim_t::interactive_fregh(const std::string& cmd, const std::vector<std::str
 void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args)
 {
   fpr f;
-  f.r = get_freg(args);
+  f.r = get_freg(args, 32);
 
   std::ostream out(sout_.rdbuf());
   out << (isBoxedF32(f.r) ? (double)f.s : NAN) << std::endl;
@@ -435,7 +449,7 @@ void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::str
 void sim_t::interactive_fregd(const std::string& cmd, const std::vector<std::string>& args)
 {
   fpr f;
-  f.r = get_freg(args);
+  f.r = get_freg(args, 64);
 
   std::ostream out(sout_.rdbuf());
   out << (isBoxedF64(f.r) ? f.d : NAN) << std::endl;
diff --git a/riscv/isa_parser.cc b/riscv/isa_parser.cc
index 6ac146b..ddb98c9 100644
--- a/riscv/isa_parser.cc
+++ b/riscv/isa_parser.cc
@@ -130,6 +130,18 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
       extension_table[EXT_ZBKC] = true;
     } else if (ext_str == "zbkx") {
       extension_table[EXT_ZBKX] = true;
+    } else if (ext_str == "zdinx") {
+      extension_table[EXT_ZFINX] = true;
+      extension_table[EXT_ZDINX] = true;
+    } else if (ext_str == "zfinx") {
+      extension_table[EXT_ZFINX] = true;
+    } else if (ext_str == "zhinx") {
+      extension_table[EXT_ZFINX] = true;
+      extension_table[EXT_ZHINX] = true;
+      extension_table[EXT_ZHINXMIN] = true;
+    } else if (ext_str == "zhinxmin") {
+      extension_table[EXT_ZFINX] = true;
+      extension_table[EXT_ZHINXMIN] = true;
     } else if (ext_str == "zk") {
       extension_table[EXT_ZBKB] = true;
       extension_table[EXT_ZBKC] = true;
@@ -229,6 +241,10 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
     bad_isa_string(str, ("can't parse: " + std::string(p)).c_str());
   }
 
+  if (extension_table[EXT_ZFINX] && ((max_isa >> ('f' - 'a')) & 1)) {
+    bad_isa_string(str, ("Zfinx/ZDinx/Zhinx{min} extensions conflict with Base 'F/D/Q/Zfh{min}' extensions"));
+  }
+
   std::string lowercase = strtolower(priv);
   bool user = false, supervisor = false;
 
diff --git a/riscv/sim.h b/riscv/sim.h
index 97cada1..c355f31 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -140,7 +140,7 @@ private:
   void interactive_until_silent(const std::string& cmd, const std::vector<std::string>& args);
   void interactive_until_noisy(const std::string& cmd, const std::vector<std::string>& args);
   reg_t get_reg(const std::vector<std::string>& args);
-  freg_t get_freg(const std::vector<std::string>& args);
+  freg_t get_freg(const std::vector<std::string>& args, int size);
   reg_t get_mem(const std::vector<std::string>& args);
   reg_t get_pc(const std::vector<std::string>& args);
 
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h
index 1a2a734..9ff383c 100644
--- a/riscv/v_ext_macros.h
+++ b/riscv/v_ext_macros.h
@@ -1802,7 +1802,7 @@ reg_t index[P.VU.vlmax]; \
     case e16: { \
       float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \
       float32_t vs2 = f16_to_f32(P.VU.elt<float16_t>(rs2_num, i)); \
-      float32_t rs1 = f16_to_f32(f16(READ_FREG(rs1_num))); \
+      float32_t rs1 = f16_to_f32(FRS1_H); \
       BODY16; \
       set_fp_exceptions; \
       break; \
@@ -1810,7 +1810,7 @@ reg_t index[P.VU.vlmax]; \
     case e32: { \
       float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \
       float64_t vs2 = f32_to_f64(P.VU.elt<float32_t>(rs2_num, i)); \
-      float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \
+      float64_t rs1 = f32_to_f64(FRS1_F); \
       BODY32; \
       set_fp_exceptions; \
       break; \
@@ -1856,7 +1856,7 @@ reg_t index[P.VU.vlmax]; \
     case e16: { \
       float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \
       float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \
-      float32_t rs1 = f16_to_f32(f16(READ_FREG(rs1_num))); \
+      float32_t rs1 = f16_to_f32(FRS1_H); \
       BODY16; \
       set_fp_exceptions; \
       break; \
@@ -1864,7 +1864,7 @@ reg_t index[P.VU.vlmax]; \
     case e32: { \
       float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \
       float64_t vs2 = P.VU.elt<float64_t>(rs2_num, i); \
-      float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \
+      float64_t rs1 = f32_to_f64(FRS1_F); \
       BODY32; \
       set_fp_exceptions; \
       break; \