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author | Scott Johnson <scott.johnson@arilinc.com> | 2022-07-15 18:06:24 -0700 |
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committer | Scott Johnson <scott.johnson@arilinc.com> | 2022-07-15 18:16:36 -0700 |
commit | 031681b2f3bfa120769d9ead1ca866ca1be163b4 (patch) | |
tree | 988b1ad9b3ad60ed5747c23a27e6b8fbff749dc9 | |
parent | 80a078f0d5dd0a9f457d23aaa36a021cd68038dd (diff) | |
download | riscv-isa-sim-031681b2f3bfa120769d9ead1ca866ca1be163b4.zip riscv-isa-sim-031681b2f3bfa120769d9ead1ca866ca1be163b4.tar.gz riscv-isa-sim-031681b2f3bfa120769d9ead1ca866ca1be163b4.tar.bz2 |
Split up misaligned load into several steps
Since the middle step is about to get much more complex
-rw-r--r-- | riscv/mmu.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 5e776a9..6d8072b 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -56,8 +56,11 @@ public: { #ifdef RISCV_ENABLE_MISALIGNED reg_t res = 0; - for (size_t i = 0; i < size; i++) - res += (reg_t)load_uint8(addr + (target_big_endian? size-1-i : i)) << (i * 8); + for (size_t i = 0; i < size; i++) { + const reg_t byteaddr = addr + (target_big_endian? size-1-i : i); + const reg_t bytedata = (reg_t)load_uint8(byteaddr); + res += bytedata << (i * 8); + } return res; #else bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags); |