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author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-31 20:39:47 +0800 |
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committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-10 23:05:35 +0800 |
commit | 793ffe508a5b81ce27f1baf2c5afb0b58a4236c6 (patch) | |
tree | c63cc0806775e5ced759ab202d187da8aa1a64c3 | |
parent | db24e31569cab07f7d91c4f417aca12fab4fd018 (diff) | |
download | riscv-isa-sim-793ffe508a5b81ce27f1baf2c5afb0b58a4236c6.zip riscv-isa-sim-793ffe508a5b81ce27f1baf2c5afb0b58a4236c6.tar.gz riscv-isa-sim-793ffe508a5b81ce27f1baf2c5afb0b58a4236c6.tar.bz2 |
Fix code indentation in processor.cc, interactive.cc, debug_module.h/cc
execute.cc, entropy_source.h and v_ext_macros.h
-rw-r--r-- | riscv/debug_module.cc | 58 | ||||
-rw-r--r-- | riscv/debug_module.h | 32 | ||||
-rw-r--r-- | riscv/entropy_source.h | 36 | ||||
-rw-r--r-- | riscv/execute.cc | 24 | ||||
-rw-r--r-- | riscv/interactive.cc | 26 | ||||
-rw-r--r-- | riscv/processor.cc | 2 | ||||
-rw-r--r-- | riscv/v_ext_macros.h | 2 |
7 files changed, 90 insertions, 90 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index a3d35ea..16520d1 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -165,18 +165,18 @@ bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes) bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes) { D( - switch (len) { - case 4: - fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=0x%08x); " - "hartsel=0x%x\n", addr, (unsigned) len, *(uint32_t *) bytes, - dmcontrol.hartsel); - break; - default: - fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=...); " - "hartsel=0x%x\n", addr, (unsigned) len, dmcontrol.hartsel); - break; - } - ); + switch (len) { + case 4: + fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=0x%08x); " + "hartsel=0x%x\n", addr, (unsigned) len, *(uint32_t *) bytes, + dmcontrol.hartsel); + break; + default: + fprintf(stderr, "store(addr=0x%lx, len=%d, bytes=...); " + "hartsel=0x%x\n", addr, (unsigned) len, dmcontrol.hartsel); + break; + } + ); uint8_t id_bytes[4]; uint32_t id = 0; @@ -215,11 +215,11 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes) } } if (dmcontrol.hartsel == id) { - if (0 == (debug_rom_flags[id] & (1 << DEBUG_ROM_FLAG_GO))){ - if (dmcontrol.hartsel == id) { - abstract_command_completed = true; - } + if (0 == (debug_rom_flags[id] & (1 << DEBUG_ROM_FLAG_GO))){ + if (dmcontrol.hartsel == id) { + abstract_command_completed = true; } + } } return true; } @@ -394,15 +394,15 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) result = set_field(result, DM_DMCONTROL_HASEL, dmcontrol.hasel); result = set_field(result, DM_DMCONTROL_HARTSELLO, dmcontrol.hartsel); result = set_field(result, DM_DMCONTROL_HARTRESET, dmcontrol.hartreset); - result = set_field(result, DM_DMCONTROL_NDMRESET, dmcontrol.ndmreset); + result = set_field(result, DM_DMCONTROL_NDMRESET, dmcontrol.ndmreset); result = set_field(result, DM_DMCONTROL_DMACTIVE, dmcontrol.dmactive); } break; case DM_DMSTATUS: { - dmstatus.allhalted = true; + dmstatus.allhalted = true; dmstatus.anyhalted = false; - dmstatus.allrunning = true; + dmstatus.allrunning = true; dmstatus.anyrunning = false; dmstatus.allnonexistant = true; dmstatus.allresumeack = true; @@ -430,8 +430,8 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) // non-existant hartsel. dmstatus.anynonexistant = (dmcontrol.hartsel >= nprocs); - dmstatus.allunavail = false; - dmstatus.anyunavail = false; + dmstatus.allunavail = false; + dmstatus.anyunavail = false; result = set_field(result, DM_DMSTATUS_IMPEBREAK, dmstatus.impebreak); @@ -439,15 +439,15 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) hart_state[dmcontrol.hartsel].havereset); result = set_field(result, DM_DMSTATUS_ANYHAVERESET, hart_state[dmcontrol.hartsel].havereset); - result = set_field(result, DM_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant); - result = set_field(result, DM_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail); - result = set_field(result, DM_DMSTATUS_ALLRUNNING, dmstatus.allrunning); - result = set_field(result, DM_DMSTATUS_ALLHALTED, dmstatus.allhalted); + result = set_field(result, DM_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant); + result = set_field(result, DM_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail); + result = set_field(result, DM_DMSTATUS_ALLRUNNING, dmstatus.allrunning); + result = set_field(result, DM_DMSTATUS_ALLHALTED, dmstatus.allhalted); result = set_field(result, DM_DMSTATUS_ALLRESUMEACK, dmstatus.allresumeack); - result = set_field(result, DM_DMSTATUS_ANYNONEXISTENT, dmstatus.anynonexistant); - result = set_field(result, DM_DMSTATUS_ANYUNAVAIL, dmstatus.anyunavail); - result = set_field(result, DM_DMSTATUS_ANYRUNNING, dmstatus.anyrunning); - result = set_field(result, DM_DMSTATUS_ANYHALTED, dmstatus.anyhalted); + result = set_field(result, DM_DMSTATUS_ANYNONEXISTENT, dmstatus.anynonexistant); + result = set_field(result, DM_DMSTATUS_ANYUNAVAIL, dmstatus.anyunavail); + result = set_field(result, DM_DMSTATUS_ANYRUNNING, dmstatus.anyrunning); + result = set_field(result, DM_DMSTATUS_ANYHALTED, dmstatus.anyhalted); result = set_field(result, DM_DMSTATUS_ANYRESUMEACK, dmstatus.anyresumeack); result = set_field(result, DM_DMSTATUS_AUTHENTICATED, dmstatus.authenticated); result = set_field(result, DM_DMSTATUS_AUTHBUSY, dmstatus.authbusy); diff --git a/riscv/debug_module.h b/riscv/debug_module.h index d79ce7d..8230557 100644 --- a/riscv/debug_module.h +++ b/riscv/debug_module.h @@ -11,16 +11,16 @@ class sim_t; class bus_t; typedef struct { - // Size of program_buffer in 32-bit words, as exposed to the rest of the - // world. - unsigned progbufsize; - unsigned max_sba_data_width; - bool require_authentication; - unsigned abstract_rti; - bool support_hasel; - bool support_abstract_csr_access; - bool support_haltgroups; - bool support_impebreak; + // Size of program_buffer in 32-bit words, as exposed to the rest of the + // world. + unsigned progbufsize; + unsigned max_sba_data_width; + bool require_authentication; + unsigned abstract_rti; + bool support_hasel; + bool support_abstract_csr_access; + bool support_haltgroups; + bool support_impebreak; } debug_module_config_t; typedef struct { @@ -54,12 +54,12 @@ typedef struct { } dmstatus_t; typedef enum cmderr { - CMDERR_NONE = 0, - CMDERR_BUSY = 1, - CMDERR_NOTSUP = 2, - CMDERR_EXCEPTION = 3, - CMDERR_HALTRESUME = 4, - CMDERR_OTHER = 7 + CMDERR_NONE = 0, + CMDERR_BUSY = 1, + CMDERR_NOTSUP = 2, + CMDERR_EXCEPTION = 3, + CMDERR_HALTRESUME = 4, + CMDERR_OTHER = 7 } cmderr_t; typedef struct { diff --git a/riscv/entropy_source.h b/riscv/entropy_source.h index 184bec7..38645ae 100644 --- a/riscv/entropy_source.h +++ b/riscv/entropy_source.h @@ -51,25 +51,25 @@ public: if(return_status == OPST_ES16) { - // Add some sampled entropy into the low 16 bits - uint16_t entropy = this -> get_two_random_bytes(); - result |= entropy; + // Add some sampled entropy into the low 16 bits + uint16_t entropy = this -> get_two_random_bytes(); + result |= entropy; } else if(return_status == OPST_BIST) { - // Do nothing. + // Do nothing. } else if(return_status == OPST_WAIT) { - // Do nothing. + // Do nothing. } else if(return_status == OPST_DEAD) { - // Do nothing. Stay dead. + // Do nothing. Stay dead. } else { - // Unreachable. + // Unreachable. } @@ -92,25 +92,25 @@ public: // Read two random bytes from the entropy source file. uint16_t get_two_random_bytes() { - std::ifstream fh(this -> randomness_source, std::ios::binary); + std::ifstream fh(this -> randomness_source, std::ios::binary); - if(fh.is_open()) { + if(fh.is_open()) { - uint16_t random_bytes; + uint16_t random_bytes; - fh.read((char*)(&random_bytes), 2); + fh.read((char*)(&random_bytes), 2); - fh.close(); + fh.close(); - return random_bytes; + return random_bytes; - } else { + } else { - fprintf(stderr, "Could not open randomness source file:\n\t"); - fprintf(stderr, "%s", randomness_source.c_str()); - abort(); + fprintf(stderr, "Could not open randomness source file:\n\t"); + fprintf(stderr, "%s", randomness_source.c_str()); + abort(); - } + } } diff --git a/riscv/execute.cc b/riscv/execute.cc index cc0d4c3..1f9ddef 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -240,18 +240,18 @@ void processor_t::step(size_t n) mmu_t* _mmu = mmu; #define advance_pc() \ - if (unlikely(invalid_pc(pc))) { \ - switch (pc) { \ - case PC_SERIALIZE_BEFORE: state.serialized = true; break; \ - case PC_SERIALIZE_AFTER: ++instret; break; \ - default: abort(); \ - } \ - pc = state.pc; \ - break; \ - } else { \ - state.pc = pc; \ - instret++; \ - } + if (unlikely(invalid_pc(pc))) { \ + switch (pc) { \ + case PC_SERIALIZE_BEFORE: state.serialized = true; break; \ + case PC_SERIALIZE_AFTER: ++instret; break; \ + default: abort(); \ + } \ + pc = state.pc; \ + break; \ + } else { \ + state.pc = pc; \ + instret++; \ + } try { diff --git a/riscv/interactive.cc b/riscv/interactive.cc index 0b71507..4e2ffb1 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -150,17 +150,17 @@ void sim_t::interactive() // first get commands from file, if cmd_file has been set if (cmd_file && !feof(cmd_file) && fscanf(cmd_file,"%" STR(MAX_CMD_STR) "[^\n]\n", cmd_str)==1) { // up to MAX_CMD_STR characters before \n, skipping \n - s = cmd_str; - // while we get input from file, output goes to stderr - sout_.rdbuf(std::cerr.rdbuf()); + s = cmd_str; + // while we get input from file, output goes to stderr + sout_.rdbuf(std::cerr.rdbuf()); } else { - // when there are no commands left from file or if there was no file from the beginning - cmd_file = NULL; // mark file pointer as being not valid, so any method can test this easily + // when there are no commands left from file or if there was no file from the beginning + cmd_file = NULL; // mark file pointer as being not valid, so any method can test this easily #ifdef HAVE_BOOST_ASIO - s = rin(&bout); // get command string from socket or terminal + s = rin(&bout); // get command string from socket or terminal #else - std::cerr << ": " << std::flush; - s = readline(2); // 2 is stderr, but when doing reads it reverts to stdin + std::cerr << ": " << std::flush; + s = readline(2); // 2 is stderr, but when doing reads it reverts to stdin #endif } @@ -391,7 +391,7 @@ void sim_t::interactive_vreg(const std::string& cmd, const std::vector<std::stri void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::string>& args) { if (args.size() < 1) - throw trap_interactive(); + throw trap_interactive(); processor_t *p = get_core(args[0]); int max_xlen = p->get_isa().get_max_xlen(); @@ -404,14 +404,14 @@ void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::strin for (int r = 0; r < NXPR; ++r) { out << std::setfill(' ') << std::setw(4) << xpr_name[r] - << ": 0x" << std::setfill('0') << std::setw(max_xlen/4) - << zext(p->get_state()->XPR[r], max_xlen); + << ": 0x" << std::setfill('0') << std::setw(max_xlen/4) + << zext(p->get_state()->XPR[r], max_xlen); if ((r + 1) % 4 == 0) out << std::endl; } } else { - out << "0x" << std::setfill('0') << std::setw(max_xlen/4) - << zext(get_reg(args), max_xlen) << std::endl; + out << "0x" << std::setfill('0') << std::setw(max_xlen/4) + << zext(get_reg(args), max_xlen) << std::endl; } } diff --git a/riscv/processor.cc b/riscv/processor.cc index 0325c51..790f18c 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -588,7 +588,7 @@ void processor_t::reset() put_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT); } - for (auto e : custom_extensions) // reset any extensions + for (auto e : custom_extensions) // reset any extensions e.second->reset(); if (sim) diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index 9ff383c..19207f7 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -56,7 +56,7 @@ static inline bool is_overlapped_widen(const int astart, int asize, if (astart < bstart && is_overlapped(astart, asize, bstart, bsize) && !is_overlapped(astart, asize, bstart + bsize, bsize)) { - return false; + return false; } else { return std::max(aend, bend) - std::min(astart, bstart) < asize + bsize; } |