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author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-17 09:13:06 +0800 |
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committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-17 09:13:06 +0800 |
commit | 61a2c0ee6306562e084b25e4734d6ae725c475b4 (patch) | |
tree | b8259cc8a4efcbd66f6b36acb6829b3db944c045 | |
parent | dd11aceaf6fb19c2e9ab549f1bcc3ae89ce1b735 (diff) | |
download | riscv-isa-sim-61a2c0ee6306562e084b25e4734d6ae725c475b4.zip riscv-isa-sim-61a2c0ee6306562e084b25e4734d6ae725c475b4.tar.gz riscv-isa-sim-61a2c0ee6306562e084b25e4734d6ae725c475b4.tar.bz2 |
extract the progress of computing the inital value of mstatus into
separate function compute_mstatus_initial_value()
-rw-r--r-- | riscv/csrs.cc | 20 | ||||
-rw-r--r-- | riscv/csrs.h | 1 |
2 files changed, 12 insertions, 9 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 6f8f260..be23a2e 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -466,15 +466,7 @@ bool sstatus_proxy_csr_t::unlogged_write(const reg_t val) noexcept { // implement class mstatus_csr_t mstatus_csr_t::mstatus_csr_t(processor_t* const proc, const reg_t addr): base_status_csr_t(proc, addr), - val(0 - | (proc->extension_enabled_const('U') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_UXL, xlen_to_uxl(proc->get_const_xlen())) : 0) - | (proc->extension_enabled_const('S') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_SXL, xlen_to_uxl(proc->get_const_xlen())) : 0) - -#ifdef RISCV_ENABLE_DUAL_ENDIAN - | (proc->get_mmu()->is_target_big_endian() ? MSTATUS_UBE | MSTATUS_SBE | MSTATUS_MBE : 0) -#endif - | 0 // initial value for mstatus - ) { + val(compute_mstatus_initial_value()) { } bool mstatus_csr_t::unlogged_write(const reg_t val) noexcept { @@ -497,6 +489,16 @@ bool mstatus_csr_t::unlogged_write(const reg_t val) noexcept { return true; } +reg_t mstatus_csr_t::compute_mstatus_initial_value() const noexcept { + return 0 + | (proc->extension_enabled_const('U') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_UXL, xlen_to_uxl(proc->get_const_xlen())) : 0) + | (proc->extension_enabled_const('S') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_SXL, xlen_to_uxl(proc->get_const_xlen())) : 0) +#ifdef RISCV_ENABLE_DUAL_ENDIAN + | (proc->get_mmu()->is_target_big_endian() ? MSTATUS_UBE | MSTATUS_SBE | MSTATUS_MBE : 0) +#endif + | 0; // initial value for mstatus +} + // implement class rv32_low_csr_t rv32_low_csr_t::rv32_low_csr_t(processor_t* const proc, const reg_t addr, csr_t_p orig): csr_t(proc, addr), diff --git a/riscv/csrs.h b/riscv/csrs.h index 500bde7..ea6d4d9 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -246,6 +246,7 @@ class mstatus_csr_t final: public base_status_csr_t { protected: virtual bool unlogged_write(const reg_t val) noexcept override; private: + reg_t compute_mstatus_initial_value() const noexcept; reg_t val; }; |