riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-08-03	declare socket properties in sim_t	Elmar Melcher	1	-1/+37
2020-11-07	Implement support for big-endian targets	Marcus Comstedt	1	-0/+2
2020-09-29	Adding symbol lookup when --enable-commitlog is enabled (#558)	sthiruva	1	-0/+2
2020-07-09	Add bootargs command-line option to Spike	Anup Patel	1	-1/+2
2020-06-16	zfh: support register dump in interactive mode	Chih-Min Chao	1	-0/+1
2020-04-27	fdt: restructure dtb create and config flow	Chih-Min Chao	1	-9/+5
2020-04-27	fdt: option: add --dtb option to specify dtb binary file	Chih-Min Chao	1	-0/+5
2020-03-27	Write execution logs to a named log file (#409)	Rupert Swarbrick	1	-7/+16
2020-02-15	Add optional support for real-time clint	Anup Patel	1	-1/+2
2020-02-14	Make spike capable of booting Linux	Anup Patel	1	-1/+3
2019-11-12	Add --priv option to control which privilege modes are available	Andrew Waterman	1	-1/+2
2019-09-18	Adds --log-commits commandline option. (#323)	dave-estes-syzexion	1	-0/+2
2019-07-22	Implement MMIO device plugins.	Aaron Jones	1	-0/+2
2019-06-18	rvv: extend interactive debug	Chih-Min Chao	1	-0/+1
2019-06-14	rvv: add varch option parser and initialize vector unit	Chih-Min Chao	1	-2/+2
2019-05-14	Clean up debug module options. (#299)	Tim Newsome	1	-3/+1
2019-04-04	Add --debug-no-abstract-csr (#267)	Tim Newsome	1	-1/+1
2019-04-02	Implement debug hasel support (#287)	Tim Newsome	1	-1/+2
2019-03-12	include sys/types.h for suseconds_t (#285)	nmeum	1	-0/+1
2018-12-13	Add --dmi-rti and --abstract-rti to test OpenOCD.	Tim Newsome	1	-1/+2
2018-10-18	Provide a noisy until interactive command	Hesham Almatary	1	-1/+3
2018-08-23	Add --disable-dtb option to suppress writing the DTB to memory	Andrew Waterman	1	-0/+4
2018-05-31	Put simif_t declaration in its own file. (#209)	Andy Wright	1	-13/+1
2018-03-16	Implement debug havereset bits	Tim Newsome	1	-0/+5
2018-03-07	Merge pull request #177 from riscv/debug_auth	Tim Newsome	1	-1/+1
2018-03-06	Narrow the interface used by the processors and memory to the top-level simul...	Prashanth Mundkur	1	-1/+12
2018-02-27	Add debug module authentication.	Tim Newsome	1	-1/+1
2018-02-01	Add --debug-sba option	Tim Newsome	1	-1/+1
2018-01-18	Support debug system bus access.	Tim Newsome	1	-2/+7
2017-12-11	Make progbuf a run-time option.	Tim Newsome	1	-1/+2
2017-11-15	Support for non-contiguous hartids	Gleb Gagarin	1	-1/+1
2017-05-16	Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10	Palmer Dabbelt	1	-5/+8
2017-05-01	Set default entry point from ELF	Andrew Waterman	1	-2/+2
2017-04-30	Add option to set start pc	Andrew Waterman	1	-1/+2
2017-04-30	Support more flexible main memory allocation	Andrew Waterman	1	-7/+4
2017-04-30	Store both host & target address in soft TLB	Andrew Waterman	1	-2/+1
2017-04-17	Merge remote-tracking branch 'origin/priv-1.10' into HEAD	Megan Wachs	1	-5/+7
2017-04-10	Implement new FP encoding	Andrew Waterman	1	-1/+2
2017-03-22	riscv: replace rtc device with a real clint implementation	Wesley W. Terpstra	1	-1/+1
2017-03-21	configstring: rename variables to dts	Wesley W. Terpstra	1	-3/+3
2017-03-21	sim: define emulated CPU clock rate to be 1GHz	Wesley W. Terpstra	1	-0/+1
2017-02-10	Entering debug mode now jumps to "dynamic rom"	Tim Newsome	1	-0/+1
2017-02-07	OpenOCD does a dmi read and gets dummy value back.	Tim Newsome	1	-1/+2
2017-02-03	OpenOCD connects, and sends some data that we receive.	Tim Newsome	1	-4/+5
2016-06-22	Remove legacy HTIF; implement HTIF directly	Andrew Waterman	1	-13/+20
2016-05-23	Have Debug memory kind of working again.	Tim Newsome	1	-3/+0
2016-05-23	Add debug_module bus device.	Tim Newsome	1	-6/+6
2016-05-23	ROM -> RAM -> ROM, waiting for debug int.	Tim Newsome	1	-0/+5
2016-05-23	Add -H to start halted.	Tim Newsome	1	-1/+1
2016-05-23	gdb can now read spike memory.	Tim Newsome	1	-0/+1