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author | Tim Newsome <tim@sifive.com> | 2017-02-03 11:29:54 -0800 |
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committer | Tim Newsome <tim@sifive.com> | 2017-02-03 11:29:54 -0800 |
commit | d1f2cf337e1a0be8eada2afadd745e1374b4a000 (patch) | |
tree | 0dd497bc9d49bd894e7cfd3afccea58a31646074 /riscv/sim.h | |
parent | e9e30598e08e4f162b523f9ef07f1510f3cfe0a6 (diff) | |
download | riscv-isa-sim-d1f2cf337e1a0be8eada2afadd745e1374b4a000.zip riscv-isa-sim-d1f2cf337e1a0be8eada2afadd745e1374b4a000.tar.gz riscv-isa-sim-d1f2cf337e1a0be8eada2afadd745e1374b4a000.tar.bz2 |
OpenOCD connects, and sends some data that we receive.
Diffstat (limited to 'riscv/sim.h')
-rw-r--r-- | riscv/sim.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 5d165c9..c8ba407 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -13,7 +13,7 @@ #include <memory> class mmu_t; -class gdbserver_t; +class remote_bitbang_t; // this class encapsulates the processors and memory in a RISC-V machine. class sim_t : public htif_t @@ -29,7 +29,9 @@ public: void set_log(bool value); void set_histogram(bool value); void set_procs_debug(bool value); - void set_gdbserver(gdbserver_t* gdbserver) { this->gdbserver = gdbserver; } + void set_remote_bitbang(remote_bitbang_t* remote_bitbang) { + this->remote_bitbang = remote_bitbang; + } const char* get_config_string() { return config_string.c_str(); } processor_t* get_core(size_t i) { return procs.at(i); } @@ -53,7 +55,7 @@ private: bool debug; bool log; bool histogram_enabled; // provide a histogram of PCs - gdbserver_t* gdbserver; + remote_bitbang_t* remote_bitbang; // memory-mapped I/O routines bool addr_is_mem(reg_t addr) { @@ -88,7 +90,6 @@ private: friend class processor_t; friend class mmu_t; - friend class gdbserver_t; // htif friend void sim_thread_main(void*); |