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author | Tim Newsome <tim@sifive.com> | 2018-03-07 17:17:39 -0800 |
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committer | GitHub <noreply@github.com> | 2018-03-07 17:17:39 -0800 |
commit | 9d1e10a36e771bf8cfbf515e07e856e021c1007a (patch) | |
tree | 949d7e13d9d2491381e510369c6ddd376e9ee739 /riscv/sim.h | |
parent | 4a97a05a6e806f7abcb6cd30685093aa5b9331a9 (diff) | |
parent | aa8cbb1ccd3856fd5e0437b0e24cfd7a3b794b8e (diff) | |
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Merge pull request #177 from riscv/debug_auth
Add debug module authentication.
Diffstat (limited to 'riscv/sim.h')
-rw-r--r-- | riscv/sim.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index 638206e..9a0a10b 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -33,7 +33,7 @@ public: sim_t(const char* isa, size_t _nprocs, bool halted, reg_t start_pc, std::vector<std::pair<reg_t, mem_t*>> mems, const std::vector<std::string>& args, const std::vector<int> hartids, - unsigned progsize, unsigned max_bus_master_bits); + unsigned progsize, unsigned max_bus_master_bits, bool require_authentication); ~sim_t(); // run the simulation to completion |