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| author | Andrew Waterman <andrew@sifive.com> | 2017-05-01 14:44:42 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-05-01 14:44:42 -0700 |
| commit | 75f2a05df9cdff6f3faba748065b3184b9f01b01 (patch) | |
| tree | 634ef6316fc2aad26ff9100f38c5367ebe30f31b /riscv/sim.h | |
| parent | 4859971a8879728378b0867e899b082e67737728 (diff) | |
| download | riscv-isa-sim-75f2a05df9cdff6f3faba748065b3184b9f01b01.zip riscv-isa-sim-75f2a05df9cdff6f3faba748065b3184b9f01b01.tar.gz riscv-isa-sim-75f2a05df9cdff6f3faba748065b3184b9f01b01.tar.bz2 | |
Set default entry point from ELF
Diffstat (limited to 'riscv/sim.h')
| -rw-r--r-- | riscv/sim.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/sim.h b/riscv/sim.h index b2181ba..421f5c2 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -31,7 +31,7 @@ public: void set_histogram(bool value); void set_procs_debug(bool value); void set_gdbserver(gdbserver_t* gdbserver) { this->gdbserver = gdbserver; } - const char* get_dts() { return dts.c_str(); } + const char* get_dts() { if (dts.empty()) reset(); return dts.c_str(); } processor_t* get_core(size_t i) { return procs.at(i); } private: @@ -95,7 +95,7 @@ private: context_t* host; context_t target; - void reset() { } + void reset(); void idle(); void read_chunk(addr_t taddr, size_t len, void* dst); void write_chunk(addr_t taddr, size_t len, const void* src); |